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verilog-AMS DFF code with initial condition (Read 3946 times)
KaNok
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verilog-AMS DFF code with initial condition
Mar 12th, 2015, 2:03am
 
Dear all,

I m designing a small verilog-ams model of DFF.

My objective is to build an DFF, with its output initial condition to be logic 'high'. When clkn is in rising edge, the output follows the input.
Here is my code.
____________________________________________________________
`include "constants.vams";
`include "disciplines.vams";
`include "compact.vams";
module cmos_latchr_lv (clk,clkn,in,out,resetn,vddlv,vsslv);
     parameter delay=1n, ttime=1n;
     output out;
     input in,clk,clkn;
     inout vddlv,vsslv;
     electrical clk,clkn,in,out,resetn,vddlv,vsslv;
     real vdvdd,vdgnd,out1;
     integer result;


analog begin

vdvdd=V(vddlv);
vdgnd=V(vsslv);
clk_thresh=vdvdd/2;

     @(initial_step)      out1 = vdvdd;
           V(out) <+ out1;
                 @ (cross (V(clkn) - clk_thresh, +1)) begin
                         
                       result=(V(in)>clk_thresh);
                 end
           V(out) <+ transition(result*vdvdd,delay,ttime);
           
     end                        
endmodule
____________________________________________________________

Now I have two questions:
1. The DFF is designed to sample the input @rising edge of clkn, but at this moment the in is not ready, how can i delay the trigger point to sample the correct input value?
2. The output initial condition is set correctly(=vddlv=0.8V), but @rising edge of clkn , it sampled the input(which is vddlv) and then output to V(out). But actually I want to output keep to 0.8V, not accumulate to 1.6V(0.8V+0.8V). How can I correct it?

Thank you very much for your guidance.
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KaNok
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Re: verilog-AMS DFF code with initial condition
Reply #1 - Mar 12th, 2015, 2:10am
 
Sorry guys, I cannot attached the simulated waveform.
How can I attached it?
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boe
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Re: verilog-AMS DFF code with initial condition
Reply #2 - Mar 12th, 2015, 2:48am
 
KaNok,
you have two contribution statements in your code. According to the language definition they are summed up.
you should use only one contribution statement (the one with the transition filter) and set result at initial_step to 1.
- B O E
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KaNok
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Re: verilog-AMS DFF code with initial condition
Reply #3 - Mar 12th, 2015, 7:24pm
 
Thanks BOE.

It works! Grin Grin
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KaNok
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Re: verilog-AMS DFF code with initial condition
Reply #4 - Mar 13th, 2015, 2:12am
 
But I still have point 2 issue,

Can I delay the trigger point with a constant value, so that
I can sample the correct result?

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boe
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Re: verilog-AMS DFF code with initial condition
Reply #5 - Mar 13th, 2015, 5:47am
 
KaNok,
how about delaying the clock signal?
- B O E
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