Now I can loss some tolerance to make it converge. But the AC/STB result is wrong.
The structure is in the attached picture. The compensation net work is not shown there.
I checked the PSS result, it seems most net are in their correct value.

I suggest that you take a look at http://www.designers-guide.org/Forum/YaBB.pl?num=1189658426.

RFIdea,

  The suggestion for longer tstab is valid. However, DC-to-DC
Converters provide some unique challenges. Other areas to
consider and investigate:

1) It is difficult to tell from the block diagram, but the clock
   generator needs to have some delay so both power devices
   are not on at the same time. Improper timing can generate
   large current spikes at the instant of switching resulting in
   convergence issues. Typically, real power devices would also
   be unhappy at the high current density.  

2) If you are including effects such as the power supply bond wire,
   then the power supply bypass network should be included. Since
   a DC-to-DC converters have negative resistance at the power
   supply input -R*L can oscillations that result in convergence
   issues.

3) Yes, loosening tolerances is also an approach that I use when
   simulating DC-to-DC Converters, however, you should check
   the waveforms to verify that they are correct, and periodic.    

  Rather than generic longer tstab, run a transient simulation and
look at the duty cycle of the DC-to-DC converter at the output of
the comparator and set tstab based on the settling of the duty cycle.

  Modeling of DC-to-DC Converters is not trivial. However if you
careful, the results can be useful.  

                                                                         Sheldon

Hi Sheldon, Ken,

Thanks for your idea.

I use a nonoverlap block to generate clock edge, so as in the real circuit, both switch won't open at the same time.
This block is where I have to use the "instrument" declare.

I read from Cadence papers, it says the function absdelay is not supported in PSS simulation. So i think this module has to be "instrument" block.

Here is the main code of my nonoverlap module:

analog begin

@(initial_step) begin
   polar1 = V(in, gnd)>vth?1:0;
   polar2 = polar1;
end

   V(net1, gnd) <+ absdelay(V(in, gnd), overlaptime*0.5);
   polar1 = V(in, gnd)>vth?1:0;
   polar2 = V(net1, gnd)>vth?1:0;
   
V(out, gnd) <+ V(vcc, gnd)*(polar1&&polar2);
V(outb, gnd) <+ V(vcc, gnd)*(!(polar1||polar2));

end

Ken,

Yes, with the RC delay. this module could run PSS now. I also changed some other modules with this method.
Now, I still has the hidden state problem in the PWM signal block. It should generate a ramp up signal with certain period.  
I think about it for several days. It seems I have to save the "state" in a variable so to tell the voltage(current) should increase(charge) or decrease (discharge), that cause the hidden state problem.

Do you give me some suggestions on such period signals?

And here is the code to describe it as voltage:

PWMvol = PWMref>V(VCC, GND)?V(VCC, GND):PWMref;

   @(timer(0, cycle)) begin
       slope = PWMvol/(cycle-falltime);
       wstart = $abstime;
       polar = 1;
   end

   @(timer(cycle-falltime, cycle)) begin
       slope = -PWMvol/falltime;
       wstart = $abstime;
       polar = -1;
   end
   
   xout = (1+polar)*0.5*slope*($abstime- wstart)+(1-polar)*0.5*(2.5 + slope*($abstime- wstart));

   V(VPWM) <+ xout;
end

Both version use variable to save state, so both failed in RF.  :'(

Hi Ken,

Yes, i got it now. There is really different direction to think about it.

1st I try to use 2 idt and idtmod. It works but I find when the simulation goes to 5mS or more, some error accumulated. The PWM signal either goes higher and higher or lower and lower. I am not sure if it is the simulator or something else wrong in my system.

Then from your explain, using $abstime should be OK for RF simulation. So I think I can use the operator % to check the time instead of save the "current start time".

Here is my code:

// VerilogA for dc_pwm, veriloga

`include "constants.vams"
`include "disciplines.vams"
module dc_pwm(VPWM, GND, VCC);
output VPWM;
electrical VPWM;
input GND;
electrical GND;
input VCC;
electrical VCC;

parameter real cycle = 20u;
parameter real falltime = 1u;
parameter real PWMref = 2.5;
parameter integer DEBUG = 0;

real xout;
real slope;
real wstart;
real wtime;
real polar;

real PWMvol;

analog begin
   @(initial_step) begin
       PWMvol = PWMref>V(VCC, GND)?V(VCC, GND):PWMref;
       wstart = 0;
       wtime = 0;
       polar = 1;
   end

   PWMvol = PWMref>V(VCC, GND)?V(VCC, GND):PWMref;//the high level of PWM singal

   wstart = $abstime-($abstime%cycle); //cycle start
   wtime = $abstime%cycle; //remain time
   polar = (wtime<(cycle-falltime))?1:-1; // rising or falling part
   slope = (polar>0)?(PWMvol/(cycle-falltime)):(-PWMvol/falltime); // slope
   
   xout = (1+polar)*0.5*slope*($abstime- wstart)+(1-polar)*0.5*(PWMvol + slope*($abstime- wstart - cycle + falltime));

   V(VPWM) <+ xout;
   
@(final_step) begin
   $strobe("Module = %M, slope = %g, wtime = %g, wstart=%g, time is %g", slope, wtime, wstart, $abstime);
end
end

endmodule