The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 28th, 2024, 2:29pm
Pages: 1
Send Topic Print
uniform distribution in verilog A (Read 3399 times)
josef_sous
New Member
*
Offline



Posts: 3

uniform distribution in verilog A
Jan 21st, 2015, 7:29am
 
hi all,
i'm new in verilog A so I've got some basic question.
well i'm trying to simulate the influence of the TDC quantization noise  in ADPLL close loop . fot that  i  want to add some quantization noise in the form of  a uniform distribution so i write this code:    
// VerilogA for adpll model, VNoiseuniform, verilog a

`include "constants.vams"
`include "disciplines.vams"

module VNoise_uniform(out);
output out;
electrical out;
parameter real half_LSB =-10e-12;   //

real noise,end_range;
integer seed;

analog begin
 @ (initial_step) begin
    seed = 0; // Initialize the seed just once
    end_range =10e-12; // A variable
 end
 noise = $rdist_uniform(seed,half_LSB,end_range);

 V(out) <+ noise;

end
endmodule  ///
well  while i'm running it on spectre   tran simulation i got something that's look like a uniform noise but when i examine the noise via noise simulation(in db) i get the lower bound that i can get ,for example i suppose to get a -224db for the value in the code and the simulation plot's is -6.5Kdb!!!
well what i'm doing wrong?
thanks !
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: uniform distribution in verilog A
Reply #1 - Jan 22nd, 2015, 7:55am
 
josef_sous wrote on Jan 21st, 2015, 7:29am:
but when i examine the noise via noise simulation(in db)


Do you know how a noise analysis works in Spice?  (Hint: it's a linearized analysis about an operating point.)

Verilog-A provides white_noise and flicker_noise for small-signal noise sources.  You might want to read about them in the LRM.

You should also read up on "transient noise" algorithms, because I suspect that small-signal noise won't show up in the PLL simulations you're planning to do.


Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
josef_sous
New Member
*
Offline



Posts: 3

Re: uniform distribution in verilog A
Reply #2 - Jan 22nd, 2015, 8:48am
 
thanks for the answer ...
i did some mess there.
what do you mean when you say:
" small-signal noise won't show up in the PLL simulations.."
i built a linear phase domain scheme using svcvs blocks , and insert relevant noise sources and i planing to examine the out-put via noise analysis . and thats will give me the calculated phase noise.
am i wright?
thanks again
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: uniform distribution in verilog A
Reply #3 - Jan 22nd, 2015, 1:38pm
 
I'm not familiar with "linear phase domain schemes."

I would think, though, that if you are describing some sort of linear system, you'll sort of be computing the gain (transfer function) from the noise injection points to the output, and you won't want to be modeling the noise as values from a uniform distribution, generating samples during a transient analysis, which is what your $rdist is doing.

What should noise look like in the phase domain?
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.