hello all!!!

i am using this code for sigma delta adc in veriloga . But the SNR of the output is low. can anyone check and suggest me the modifications.

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// VerilogA for decimation, sdm, veriloga

`include "constants.vams"
`include "disciplines.vams"


module sdm(in,clk,out);

input in,clk;
output out;
voltage in,clk,out;


parameter real clk_vth=0.9;
parameter alpha = 0.5;
parameter beta  = 0.5;


real int1_out;   /// variable-- not connection with the outside world
real int2_out;
real dac_out;
real mix1_out;
real mix2_out;
real t_int1_out;
real t_int2_out;
real sdm_out;


analog
begin
 @(initial_step)
 begin

   int1_out = 0.0 ;
   int2_out = 0.0 ;
   dac_out  = 0.0 ;
   mix1_out = 0.0 ;
   mix2_out = 0.0 ;
   sdm_out  = 0 ;
   t_int2_out  = 0 ;
   t_int1_out  = 0 ;
 end

 @(cross(V(clk) - clk_vth,1))
 begin
  mix2_out   = int1_out - dac_out ;
  int2_out = t_int2_out + beta*mix2_out ;
  t_int2_out = int2_out ;
  mix1_out   = V(in)    - dac_out ;
  int1_out = t_int1_out + alpha*mix1_out ;
  t_int1_out = int1_out ;

    if (int2_out >= 0.0) sdm_out = 1.8 ;   // ADC-- comparator
    else                 sdm_out = 0 ;

  if (sdm_out == 0)    dac_out = 0.5 ;
  else                 dac_out =  1.3 ;
 end
 V(out) <+ sdm_out ;
end
endmodule

sigma-delta ADC's high SNR comes from a noise shaping filter. I do not see it in your design yet.