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MOS layout for RF: Source/Drain Area & perimeter (Read 1807 times)

clidre

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MOS layout for RF: Source/Drain Area & perimeter
Dec 13^th, 2014, 11:13am

Hello,
I'm a newbie in RF design. I'm layouting an inverter that works at 2.5GHz. I've noticed that in the technology I'm using, there's the possibility to produce individual RX shapes in device layout, thus increasing the pd (dran perimeter) and ps (source perimeter). Do you know what is the advantage to do that? Is it useful for RF?
Thanks!

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: MOS layout for RF: Source/Drain Area & perimeter Reply #1 - Dec 13^th, 2014, 3:45pm Hi, I am not an expert but guessing. By changing perimeter&&Area we could trade diffusion capacitance and od drain resistance. In LDO I have seen people have been using extended drain to move drain contacts far from poly to reduce Cgd for better psrr.. Thanks, Raj.
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