The Designer's Guide Community
Forum
ForumVerilog-AMSAnalysisModelingDesignTheory
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 16th, 2024, 10:51am
 
  HomeHelpSearchLoginRegisterPM to admin    
The Designer's Guide Community Forum › Modeling › Behavioral Models › Modeling dependent current source.
‹ Previous topic | Next topic ›
Pages: 1
Send Topic Print
Modeling dependent current source. (Read 2912 times)
anas.iftikhar
New Member
*
Offline



Posts: 3
Pakistan
Modeling dependent current source.
Nov 29th, 2014, 3:10am  
Hi,

How should I model a voltage-controlled-current source in Verilog-A?
Need help.

Regards.
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: Modeling dependent current source.
Reply #1 - Jan 5th, 2015, 1:04pm  
What have you tried?  How complicated is the equation?

This is a vccs:

I(a,b) <+ V(c,d);
Back to top
 
 
If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
‹ Previous topic | Next topic ›
« Home ‹ Board
The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.