RobG wrote on Nov 3rd, 2014, 3:41am:boe wrote on Nov 3rd, 2014, 1:46am:RobG,
the standard circuit you propose applies full VDDH across the oMOS gate oxide (GS); so they require some protection if the are 5V gates.
- B O E
Whoops, you are correct. I didn't see the vgs requirement.
That's right. The circuit you proposed cannot be used in my case.
Just as a summary, see the attached picture.
I worried about the current flowing in the resistor divider, but it is not as bad as I thought. 500 uA for 100 kHz output signal works perfectly. Input capacitance of transistors is on the level of few fF. Very big transistors can achieve the input capacitance equal to single pF, but the chosen current of the voltage divider can turn on/off the PMOS relatively fast.
The only remark I have is the fact that, when output goes low, there can be undershoot on the gate of PMOS and its gate-source voltage can go lower than 25 V. It can be solved simply by driving output PMOS and NMOS transistors using no overlaping clock.