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Verilog A model of TFET (Read 4445 times)
zulqar
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Verilog A model of TFET
Oct 10th, 2014, 11:28pm
 
Hi All,
I am using verilog A model of TFET from Penn State University which is given below.
`include "constants.vams"
`include "disciplines.vams"
module NTFET(d,g,s);
inout d,g,s;
electrical g,d,s;
real Ids, Cgs, Cgd, Qs, Qd,Qg;
parameter real W=1; //Device width
analog begin
Ids=$table_model(V(d,s), (V(g,s)), "IdVg-NTFET_Lg20nm.tbl","1LL,1LL");
Cgd=$table_model(V(d,s), (V(g,s)), "CGD-NTFET_Lg20nm.tbl","1LL,1LL");
Cgs=$table_model(V(d,s), (V(g,s)), "CGS-NTFET_Lg20nm.tbl","1LL,1LL");
if(analysis("dc")) begin
I(d,s) <+ 1*Ids*W;
end
else begin

if(analysis("tran")) begin
Qd = (-1*W*Cgd)*(V(g,d));
Qs = (-1*W*Cgs)*(V(g,s));
Qg=-1*(Qd+Qs);
I(d,s) <+ 1*Ids*W ;
I(d) <+ ddt(Qd);
I(s) <+ ddt(Qs);
I(g)<+ ddt(Qg);
end
end
end
endmodule

This is basically a table driven model . DC and transient analysis has been done . I want to do ac analysis with this model . If anyone could help me regarding this , I will be thankful.

Thankls
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Ken Kundert
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Re: Verilog A model of TFET
Reply #1 - Oct 11th, 2014, 8:29am
 
You do not have to write a model for each analysis. Just use: Code:
`include "constants.vams"
`include "disciplines.vams"
module NTFET(d,g,s);
inout d,g,s;
electrical g,d,s;
real Ids, Cgs, Cgd, Qs, Qd,Qg;
parameter real W=1; //Device width
analog begin
    Ids=$table_model(V(d,s), (V(g,s)), "IdVg-NTFET_Lg20nm.tbl","1LL,1LL");
    Cgd=$table_model(V(d,s), (V(g,s)), "CGD-NTFET_Lg20nm.tbl","1LL,1LL");
    Cgs=$table_model(V(d,s), (V(g,s)), "CGS-NTFET_Lg20nm.tbl","1LL,1LL");

    Qd = (-1*W*Cgd)*(V(g,d));
    Qs = (-1*W*Cgs)*(V(g,s));
    Qg=-1*(Qd+Qs);

    I(d,s) <+ 1*Ids*W ;
    I(d) <+ ddt(Qd);
    I(s) <+ ddt(Qs);
    I(g)<+ ddt(Qg);
end
endmodule 


and it will work in all the analyses.

This model is capacitance based rather than charge based and so will exhibit severe charge conservation problems. You should integrate the capacitance with respect to voltage and build new tables that hold the charge as a function of voltage, and then use those.

-Ken
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zulqar
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Re: Verilog A model of TFET
Reply #2 - Mar 14th, 2015, 5:22am
 
I will be thankful to you if you could help me clearing one more doubt.
As it is a table driven model , so length is fixed to Lmin. Width is also initiated as W=1.
If I want to use this model for different values of W/L , then what are the expressions which I need to change in the code.
Secondly is there any possibility to use fractional aspect ratios?
Thanking you in anticipation.  
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Geoffrey_Coram
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Re: Verilog A model of TFET
Reply #3 - Mar 19th, 2015, 6:39am
 
If you want different lengths, then I suspect you may need to measure those devices and generate tables for those lengths.  Eg, for 40nm,
"IdVg-NTFET_Lg40nm.tbl"

This model was uploaded to nanoHUB, which has a compact modeling area:
https://nanohub.org/publications/12

I posted a "wish" that the authors do what Ken was suggesting (I hadn't seen his post here when I posted the wish), but the authors haven't responded.
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