Is there any way to have a fixed time step in Verilog-A?
I know $bound_step can limit the time step to a certain amount, but it does not guarantee the time step is fixed if I understand correctly.

Actually I just want to implement something like this:
Y = Y + dYdt*timestep

I know Y=idt(dYdt, 0) can do it, but at some events I also need to directly modify Y, and idt() is an analog operator that is not allowed to do so.
Any suggestions?

Thanks for explaining why there is no fixed time step.
The reset argument of idt cannot help, and I've already come up with a way to solve this problem, which is to separate the total Y into two variables.
One is the idt(), and the other one is the modification.