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ywguo

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Posts: 943
Shanghai, PRC

A stimulus for digital signal using verilog-A
Oct 04^th, 2014, 6:45am

Hi Guys,

Is it possible to write a stimulus for digital signal using verilog-A? For example, a short verilog code is shown below.
Code:

/clock generator
  initial begin
	sclk_int = 1'b0;

	forever begin
	    #(40/2) sclk_int = ~sclk_int;
	end
  end

  initial begin

	 sdata = 1'b0;

	 #2000
	 sdata_master = 1'b1;
	 sclk  = 1'b0;

	 #500
	 repeat (1) @(sclk_int);
...

Thanks a lot.
Yawei

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patrick Junior Member Offline Posts: 30 Santa Rosa, CA.	Re: A stimulus for digital signal using verilog-A Reply #1 - Oct 5^th, 2014, 1:01pm Perhaps something like: `include "disciplines.vams" module clkgen(p); output p; electrical p; reg sclk_int; initial begin sclk_int = 1'b0; forever begin #(40/2) sclk_int = ~sclk_int; end end analog begin V(p) <+ transition(sclk_int,0,1n,1n); end endmodule
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ywguo

Community Fellow

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Posts: 943
Shanghai, PRC

Re: A stimulus for digital signal using verilog-A
Reply #2 - Oct 5^th, 2014, 9:33pm

Hi Patrick,

Reg is not allowed in verilog-A.

Quote:

Warning from spectre during AHDL compile.
WARNING (VACOMP-1086):
"/project/..../clkgen/veriloga/veriloga.va",
line 10: `reg' is not a reserved keyword now but will be one in a
future release. Parsing `reg' as an identifier for now.
Error found by spectre during AHDL compile.
ERROR (VACOMP-2259): "reg sclk_int;<<--? "
"/project/..../clkgen/veriloga/veriloga.va",
line 10: syntax error.
ERROR (VACOMP-1592): "#(40<<--? /2) sclk_int = ~sclk_int;"
"/project/..../clkgen/veriloga/veriloga.va",
line 15: invalid #line directive.
ERROR (VACOMP-1814): Maximum allowable errors exceeded. Exiting AHDL
compilation....

Best Regards,
Yawei

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patrick Junior Member Offline Posts: 30 Santa Rosa, CA.	Re: A stimulus for digital signal using verilog-A Reply #3 - Oct 5^th, 2014, 9:38pm ok, I assumed you wanted to write a mixed domain model. You will need to stick to the VA analog block and analog initial block; initial block and digital syntax is not allowed in Verilog-A.
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boe Community Fellow Offline Posts: 615	Re: A stimulus for digital signal using verilog-A Reply #4 - Oct 6^th, 2014, 1:17am Ywguo, this can be done using the timer function. For examples see the Oscillator models in the Verilog-AMS section of this web site. - B O E
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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: A stimulus for digital signal using verilog-A Reply #5 - Oct 6^th, 2014, 9:33pm Hi B O E， That's a good idea. Thank you very much. Yawei
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