Hi,
I am trying to do a "Verilog - A " model of a block which takes in a control voltage (duty cycle = d ) and a 50% duty cycle clock. as input. The output of this block is a clock with duty cycle 'd'.
I am not able to figure out how to go ahead with this problem.
I have looked into the following post
http://www.designers-guide.org/Forum/YaBB.pl?num=1138941612/15Please advise
Thanks
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