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Tones in simple T&H (Read 8205 times)
SNIKE
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Tones in simple T&H
Sep 02nd, 2014, 8:39am
 
Hi all,

I am designing a 12Bit cyclic. I am trying to get away with simple Sample and hold.[ No boot strapping]. This is highly area sensitive application.
I am using bottom-plate sampling.
The input is at X Hz and my Sampling rate is 4X Hz.
My pulse width of  Sampling operation is 12 times shorter than hold operation.

I am trying to see if I can get away with simple bottom plate sampling.
I created a test bench with "Single ended" version.

I did my due diligence in finding the right switch size for 13 Bit settling.

When I do a FFT plot I see my SFDR is very bad. It is around 40dB.
My ENOB is good.

I have attached the FFT. Can someone tell me what is causing this tones, especially near the signal? Do you think differential implementation will get rid of these tones?
Are these tones due to "linear" Charge injection of bottom plate switch? Are these due to clock injection? How can I tell by just looking at the FFT.

Thanks
Snike.


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boe
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Re: Tones in simple T&H
Reply #1 - Sep 2nd, 2014, 8:53am
 
SNIKE,
where in you plot are the (folded) harmonics of the input signal?
- B O E
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SNIKE
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Re: Tones in simple T&H
Reply #2 - Sep 2nd, 2014, 11:06am
 
BOE i did-not get your question.

My signal is in bin 4096, and few bins around it [I am using a Hann window] . I am only showing plot till fs/2.

Thanks
Sai
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carlgrace
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Re: Tones in simple T&H
Reply #3 - Sep 2nd, 2014, 11:28am
 
At a first look this might be switch distortion.  Are you converting ac signals with your cyclic ADC?  If it is a dc ADC the distortion might not matter and you can reduce area by making the sampling switch small.
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SNIKE
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Re: Tones in simple T&H
Reply #4 - Sep 2nd, 2014, 12:00pm
 
Hi Carl,

My signal is a sin wave around 500KHz.

Thanks for the input. I did-not actually consider Error due to magnitude attenuation and phase shift in the steady state response.
In my settling equations I just sized the switch to meet DC step response requirement.

I think its a good point. I will size my switch more and see if this behavior improves.

Will keep you updated.

Thanks
Sai.
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SNIKE
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Re: Tones in simple T&H
Reply #5 - Sep 2nd, 2014, 12:14pm
 
BTW why do I have similar distortion at DC and Fs/2?
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Re: Tones in simple T&H
Reply #6 - Sep 2nd, 2014, 1:48pm
 
Now that you say that your input frequency is 500 kHz I think the problem is most likely quantization related.  Your input signal is 1/4th your sampling rate so the assumption that the quantization noise is white is not true anymore.  So, the errors are highly correlated with the signal --> tones in output spectrum.  

You should choose your input frequency such that there are no common factors between the input frequency and the sampling rate.

You don't want to use a window when testing an ADC because spectral leakage can totally screw things up if you're not careful.  Check out this really useful app note from Maxim explaining the situation:

http://www.maximintegrated.com/en/app-notes/index.mvp/id/1040

It's possible your ADC is fine as is.
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SNIKE
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Re: Tones in simple T&H
Reply #7 - Sep 2nd, 2014, 4:59pm
 
Hi Carl,

The frequency I picked for simulation was actually a prime number.
The fin was 497977 Hz. [I did-not give exact number to avoid confusion , hence used term around 500KHz].

So I am confident the noise is still white.

I was using windowing to avoid spectral leakage due to "non complete" cycles of Input signal.

I will try not using windowing and see if results are better.

Thanks
Sai


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Re: Tones in simple T&H
Reply #8 - Sep 2nd, 2014, 6:25pm
 
Hi,


Is there any reason not to use a whole number of input cycles? What I usually do to calculate my input frequency is take the sampling rate and multiply by n_prime/2^m, where n_prime is a prime number, and m is an integer. For example, if my sampling rate is 1 MHz, and I want roughly Fs/4, then I could do Fin = 7/32*Fs or 17/64*Fs. You would then simulate the circuit for 32 or 64 samples...

If you don't want to have complete input cycles, then you need to simulate a very large number of input cycles so that the spectral spreading has time to roll off according to your windowing function. For a high resolution, I don't think this is the way to go...

Anyway that's my understanding on the matter. Correct me if I'm wrong.


Aaron
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« Last Edit: Sep 2nd, 2014, 10:29pm by aaron_do »  

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SNIKE
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Re: Tones in simple T&H
Reply #9 - Sep 2nd, 2014, 11:34pm
 
I took the suggestions and stopped using windowing.

Now I have integer number of cycles [2011 cycles] also input frequency is
Fs*2011/8329. The FFT has many tones.

Also I replaced cmos switches with "ideal" switches. That simulation looks fine. I also attached that plot.

Can some one tell me why I am having so many tones when I use CMOS switch.  What is causing these? Can someone comment on why the FFT looks so?


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SNIKE
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Re: Tones in simple T&H
Reply #10 - Sep 2nd, 2014, 11:35pm
 
This FFT is with CMOS switch.
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carlgrace
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Re: Tones in simple T&H
Reply #11 - Sep 3rd, 2014, 5:41am
 
Hi Sai,

Well it sure looks like the issue is the switches.  Most likely there is an issue with the sizing.  One idea is to do a DC sweep and look at how the impedance changes over input swing.  See if the on-resistance of the switches changes a lot.  That could be the problem.

Another way to test this is to do the transient analysis with a very small input swing.  

Also, what happens if you increase the gate drive of the input switches (this is ok in simulation!).  If there is a dynamic issue with the switches then you will see it go away if 1. you use high gate drive, and 2. small input swing.

I think the fact the output spectrum is clean with ideal switches is very good news!

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SNIKE
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Re: Tones in simple T&H
Reply #12 - Sep 4th, 2014, 10:36am
 
Hi Carl,

I found the issue. My OTA had too much bandwidth and slew rate.
In the non-overlapping phase the output was Swinging a lot [OTA is in openloop]. I am guessing this is corrupting my virtual ground due to Cds capacitance. I need to hack my netlist to make sure this is the reason.
After I reduced the OTA bandwidth and Slewrate the FFT looks much cleaner.
I still don't like couple of tones which are at 80dB level close to Input signal. I am debugging them now.

One question is why do people use bootstrapping if bottom-plate sampling is good enough?
I have seen lots of publications with front-end bootstrapped switches.
Did you use bootstrapping in your design?

Thanks
Sai
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carlgrace
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Re: Tones in simple T&H
Reply #13 - Sep 4th, 2014, 8:23pm
 
Glad to hear it!

Bootstrapping is one of those things in your bag of tricks that you should only use if you have to.  I've never used it on a design I've taped out because I've never had to.  You only really need it if your process doesn't have low-vt devices or you have extreme input swing or distortion requirements.  

I don't entirely understand what the issue was... I'm guessing the slewing was causing your opamp to saturate?
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SNIKE
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Re: Tones in simple T&H
Reply #14 - Sep 4th, 2014, 10:19pm
 
Hi Carl,

This is a third order effect.
I have the following setup.
Ideal Opamp with Unity gain bandwidth of 10GHz.
Also have "parasitic" capacitance at the input node. [50fF].

I have 3 switches controlled by phase1, phase1early, phase2.
Phase1early opens up first [bottom plate]. Phase1early switch is the feedback switch.
Phase1 opens up after some nonoverlap time. [Phase1 is the top plate sampling switch]
Phase 2 closes after additional nonoverlap time. [Phase2 is flip around switch].

when the phase1early is closed ,input parasitic is at the virtual ground.

during the nonoverlaptime [phase1early is opened , phase1 is still closed]. In this mode you have input connected to sampling capacitance, and the second node of capacitor connected to input of opamp.
This forms a capacitive division of input signal at the input of opamp[ only during this non overlap time].

Since the opamp has bandwidth faster than nonoverlap time, the opamp amplifies the divided voltage in openloop. since the opamp has large  openloop gain, output is a gained up version of input.
Now because of parasitic CDS of phase1early switch, there is a small coupling of output to input node.
Hence the charge conservation is lost. Also this error is highly proportional to input causing non linearity.

The solution was easy, I reduced the non overlap time and reduced the opamp bandwidth to realistic value of 100MHz.

Let me know if this is not clear. I can try drawing some figures.

Thanks
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