Dear all,
I have been looking at a paper with high psrr band gap located at

http://sms.unipv.it/~franco/ConferenceProc/188.pdf

Basically I didn't get the main point here to improve PSRR. I have attached fig 3 here. basically at low frequency low takes hence good psrr, but at high frequency(near to bandwidth) Vc2 will be coupled vdd through Cgs3, but here the same thing got enhanced by Mn42. With the above argument I didn't understand what is the need of MN41,MN42, infract this additional stage will introduce systemic error.

Can any one please explain in-briefly how this is improving psrr?

Thanks,
Raj.

Hi,
I know bram nauta noise cancelation technique, but some I couldn't understand this in that way. In any -ve feedback we can find some kind of subtraction.

Coming to the circuit one thing I didn't understand. To have better power supply behaviour some one has to adjust gate of M2 to deltavdd(1+1/(Gm3*R03)) to cancel properly. For the frequency below Loop-Bandwidth opamp does this job properly, this is the reason why we have very good psrr in any feedback ckt(around 50dB), but the main question is how to get better PSRR around the BW, since no one is there to change M3 gate (except Cgs3). You are also concluding that this techniques also work below BW then improving opamp and this technique doesn't have any difference. What do you say?

Same idea has been implemented for LDO also   here..http://ee.sharif.edu/~elec3/Regulator/0759hoon.pdf

Thanks,
Raj.

I remember using this circuit some years ago, when I was having the opamp second stage as NMOS CS. And the paper too talks about having NMOS CS as the second stage where the relative cancellation of Vdd PSRR is bit bad. And if there is sufficient separation between your Amp's BW and your Cgs correcting for Vdd PSRR then this would be the fastest loop to correct it.

Hi,


without the author's additional circuitry, the PSRR would be limited by the bandwidth of the Op-Amp. The additional circuitry tracks the source voltage of the PMOS, i.e. the power supply, and applies it to the gate voltage of the PMOS. With VGS = 0 in the PMOS, no current will flow (i.e. PSRR is good).

I believe that this tracking circuit (MN41 and MN42) is intended to work independently of the Op-Amp, and so is not limited by the op-amp's bandwidth. At high frequency (beyond the op-amp GBW), assume the Op-Amp is cut-off and the AC gate voltage of MN42 is zero. Then the AC voltage at Vc2 is determined by the gain through MN41 (equal to 1) from the power supply. i.e. the PSRR can be boosted well beyond the GBW of the op-amp. It is no substitute for the op-amp because as you all pointed out, the op-amp provides significantly better DC PSRR.

Actually I think normally to get high frequency PSRR, you would add a cap from VC2 to VDD, but in this case it would degrade the op-amp's GBW.


regards,
Aaron

EDIT: I think RobG was pretty much thinking along the same lines. Its not so much a cancellation as having the gate voltage track the source. I agree that having the NMOS bias the PMOS wouldn't necessarily be a good match, but I think the only purpose is to have an AC gain of 1 for the tracking circuit, so in that respect, the NMOS are faster than PMOS.

raja.cedt wrote on Aug 28^th, 2014, 3:06am:


Bear in mind I'm reluctant only because I haven't had time to figure out how it works. With his idea the opamp output now sees Vgs of MN41, which is removed once from Vdd variations. I'm not sure that the benefit isn't just from doing that. Plus it hasn't been too much of an issue for me to get 100dB of DC rejection so I'm not included to solve a problem I've never had . However, it might be a fine idea.

Regarding tying the resistors together - M2 and M3 are used to create equal current, but they contribute thermal noise. The noise can be reduced by making their Vgs-Vt larger, but you run out of headroom. It turns out the optimum way to use this headroom is to use identical resistors - they are already dropping ~600mV which is enough. The down side is that it uses more area. I'm sure you have seen the result before:


My concern with using MN41 to bias M2 and M3 is over corners. The current in MN42 will need to change a lot to provide the proper bias for M2 and M3. This may affect the stability of the loop. It is already on the edge since he has two poles in the opamp and another in M2 and M3.

For good AC power supply rejection I would compensate the opamp with a cap and resistor in series between VC2 and VDD. (The resistor adds a zero to cancel the first pole). This will help AC rejection assuming the cap between VC2 and VSS is small. This won't work well with a two-stage opamp so instead of the miller opamp I would use a folded cascode with a PMOS input pair.

[edit... sorry for all the edits after my original posts. I seem to be making more typos and confusing statements these days.]

loose-electron wrote on Aug 28^th, 2014, 1:10pm:


That makes sense.  I'm a pretty conservative designer so all three of the bandgap references I've designed used the standard textbook architecture because it was good enough.  I think this is a good lesson for younger designers.... only innovate or use a tricky circuit when you must.

I think for this circuit, loose-electron is right, but more generally speaking, I think the idea of tying the current mirror's gate to its source by active means has merit and could find application in some circuits.


Aaron

This particular "add on" consisting of an nmos driver and a diode connected pmos load is called a substractor as already pointed out. Although i have not used it in case of a bandgap ,i have used this for a high psrr LDO and it works great. Think of it this way: The opamp path for restoring the output is slow, the direct path provided by the gate of diode connected transistor provides a very fast path for replicating the ripples on the supply, on the pmos diode connected tran and hence the bandgap or ldo pmos transistors.Hence ac psrr would be better. for the bandgap in question,what is the PSRR target?