Hello all,
            I am designing LNA with every element on-chip in 65nm technology (refer figure). With only RC extraction, |Z22|=1.1K. However, when RLCK extraction is done for 2.14GHz, |Z22| is drastically getting reduced to 390 Ohms though Ld, Ls and Lg are placed far from each other. Due to that LNA gain is becoming worse. Is this the problem with  RLCK extraction ? How come parasitic inductance and its mutual inductance can degrade output impedance by such a value? Can you suggest how degradation of |Z22|  can be avoided?

Hi,
Did you consider paracitic inductance between M2 drain and Ld, I guess that resonance frequency has gone down as aaron_do said. Please try to plot o/p impedance and see the shift in centre frequency...

Thanks,
Raj.

Hello Aron and Raja,
        Thanks for your reply. Resonant frequency is perfect. I have attached the figure where I have increased ld from 12nH to 18nH. And |Z22| increased from 390 to 640. I took the details from the extraction.
From M2 drain to Vout: 54pH + 39fF
From Vout to Ld: 263pH+26fF (Here I purposefully increased length from Vout to Ld to increase impedance)
At Vdd line: 225pH+20fF

Whether these values degrading so severely? So how can I find out impedance transformation with this?

Ps: I have attached layout in the reply below.

Regards,
Vinay

Hi,


a few comments.

1) when you increased Ld, your Rout increased. This suggests that maybe your inductor Q is the bottleneck. Try using a higher-Q inductor. I originally thought it might be feedback, but you mentioned moving Ld away didn't help...

2) The reason I suggested using Y-parameters instead of Z-parameters is because your output network is better modeled by parallel RLC. With Y-parameters, the real part will be less frequency dependent.

3) Based on the direction of the metal turns for Ld, the long line from OUT to Ld is decreasing your overall inductance, not increasing it. Unless I'm viewing it wrongly, it appears that the currents are flowing in opposite directions.

4) Are those blue lines ground shields? I assume that you're not showing us some of the layers right? I would do a study to see how effective those ground shields are.

5) Your final design is going to have a non-negligible inductance from VDD to ground because they are far away from each other. Eventually they need to get to a point where they can couple nicely together. Just FYI...

6) The connections between your inductor shields are forming a rather large short-circuit loop. This should be avoided as any current coupling to the loop will burn up in the loop's resistance. Its a good way to de-Q inductors. In your case, it may not have too much effect (would have to simulate). For grounding separate blocks, star connections are best if possible, but if not, I would use thick grounding lines to keep the impedance low.  

7) I've never actually used the Assura inductance extraction. Is that what you're using? I'm not sure how accurate it is. You could try comparing it with something like ADS momentum...


regards,
Aaron


edit:
Just noticed that those blue lines surrounding your inductors seem to be unbroken. If that's true then see point 6.

Hi Vinay,


I think you need to be careful here. Simply moving the inductor in one direction or another may reduce one effect and increase another. As much as possible you should try and isolate the effects. I suggest the following.

1) split up your layout into a few sections. The Ld network, the Lg network, the Ls network, and the transistors.

2) extract the individual networks one by one and gradually replace the ideal components with extracted ones.

3) finally add all components into one layout. This will reveal any coupling.

Regarding your other questions.

1) To get higher inductor Q, you need to design the inductors yourself.

2) Up to you. To me there are four possibilities.
a) There is some impedance transformation. But looking at the trace lengths and the sizes of your inductors, I doubt this would have such a great effect. If I remember correctly, impedance transformation wouldn't change the "available" power at the output, so you can look at that to verify.
b) Your inductors are being de-Q'd. Make sure there are no large closed metal loops as these will kill your inductor Q. Especially in the ground shields.
c) There is some feedback. Coupling between your inductors could result in feedback which would reduce your gain.
d) There is a problem with your extraction. Try using an EM simulator for the inductors and traces.

3) I made a slight mistake here. Increasing that line would indeed increase Ld, but not so effectively, as the mutual inductance between Ld and the OUT-Ld trace appears to be negative in your case. This is not good because it lowers the Q of the inductors. If Ld turns in the opposite direction, you should be able to get even higher inductance and better Q. But because the trace is small, the effect may also be small.

4) Make sure there are no closed loops in the ground shields. I'm sure you've heard of eddy currents...

5) VDD and GND are both considered to be AC ground. At AC they should be the same net, and so its good to have strong coupling between them. That's the general rule anyway...

6) There definitely appears to be a loop in between the three inductors formed by the connections between the ground shields. I cannot stress enough how amazing this book is,

http://www.amazon.com/Signal-Power-Integrity-Simplified-2nd/dp/0132349795/ref=la...

its by Eric Bogatin and its called Signal and Power Integrity Simplified. It will answer all of your questions for you and everybody will think you're half man, half amazing

7) I'm not really sure about the difference between Calibre and Assura. For L and K extraction I've only used EM simulators.


cheers,
Aaron

Hi Vinay,


For your circuit, the inductors are much larger than the trace inductance. So trace inductance is unlikely to have any effect. So it may not be necessary to use EM simulators for the inductors. Regarding your points,

3) You mentioned something about deliberately extending that wire to increase inductance. If you don't want it to affect the performance then you shouldn't do this. On the other hand, if you want to increase the inductance, it seems to me that its better to keep the wire close to the inductor, or simply use an inductor with an extra half turn.

4) You could route VDD on top of GND, and keep the bonding wires adjacent to each other. In your case they are on opposite sides of the chip (see my figure). The effect may not be so great as you will have a ground plane on the PCB, and you are using very large inductors anyway. But its something you should consider.

5) See my figure. As I mentioned before, by joining all of the ground shields, you may be creating a closed loop. The size depends on where the break is in your ground shields. This kind of closed loop can de-Q your inductors. I'm just guessing there's a loop here as it seems so from the figure.

Another thing I'm not so sure about is whether the ground shields really help. Maybe somebody else could weigh in. I think the idea is that if there's any substrate noise from other blocks, it will couple to the ground shield instead of the inductors. But in your case, the same ground is used to bias your transistor bodies. It may be that the ground shields need their own bondwire. I'm not really sure...


cheers,
Aaron


regards,
Aaron