tdlrali wrote on Jul 23rd, 2014, 7:10am:Hi all,
I'd like to use either Verilog or VHDL to describe testbenches in Virtuoso (IC6.1.5). I've successfully simulated a VerilogA module in spectre, but still I have a few questions.
1) Does Spectre only support VerilogA? Do I have to use the AMS simulator (from IUS) to use VerilogAMS / VHDL-AMS?
Yes.
Quote:2) What's the status/support of the different languages - VerilogA, VerilogAMS, VHDL-AMS? Ideally, I'd like to use VHDL-AMS, because I personally like VHDL better than Verilog.
In principle, Cadence supports both Verilog-A(MS) and VHDL-AMS. However, not everything that is in the LRMs will be supported (and there may be differences between the two language groups).
Quote:3) Can I use generic port widths? The Virtuoso Schematic Editor does not seem to support this...
I do not think you can do this with Virtuoso Schematic Editor. But if you do not need a schematic (i.e. use such cells in HDL code only), you can.
- B O E
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Virtuoso & Verilog/VHDL (Read 3600 times)