jockeymonto wrote on Jul 26th, 2014, 5:49am:Hi loose-electron, Thanks for your input. I read your article...if one takes care of all the suggestions you have mentioned, he can come up with a rigorous design. I will look into all the things you mentioned during my design. And BTW i am still at schematics level simulations stage.
I have a question about mismatch. Since I am using DAC capacitive array in my SAR ADC, I have multiple unit capacitors connected in parallel. Is it true that connecting devices of same size (like unit cap in DAC array) in parallel reduces the amount of mismatch? I have no calibration circuit till now but i have run MC simulations several times on my ADC but the resulting Vin/Vref for different runs at room temperature varies around 4-5 LSBs (0.2mV) about its nominal value. (I am using an ideal comparator right now, so the major mismatch source is the DAC capacitive array)
As a general rule, scaling the geometry up in size or increasing the numbers of devices in a matched array does improve matching.
However, beyond a certain degree the matching improvement reduce. For size scaling (the resistor body goes from 2um to 6um lets say) the matching accuracy will not be a linear curve.
Get the matching data for your foundry process.