Dear Designer's Guide Team.

I have a verilogams module.
I want to use the @(final_step) built in event to check "only once at the end of simulation" if the value of a signal is high or low (1'b1 or 1'b0).
The restriction is that I want to use this inside the digital context i.e. not inside an analog begin...end  block.

Why?
The module generates a log file, which is defined in the digital context and I am writing some data in that log file inside the digital context. In other words, that variable belongs to the digital context.
I can use the @(final_step) inside the analog context, but I cannot write data to the log file because the analog context can read but not write that "digital" variable.

Of course I can define another log file into the analog process, but I want to avoid this, I want to avoid that for every module not one but two log files need to be checked.


Explanation of the code

I want to monitor if an analog signal is inside a given range.
There is an internal variable vdda_v_flag which is initially 1'b0 and becomes 1'b1 if the analog signal to be monitored enters into the defined ranges and this variable vdda_v_flag remains 1'b1 in such a case.
If the analog signal never enters into the defined ranges, then the variable vdda_v_flag remains 1'b0.

The code looks like this:

   parameter real vdda_v_HiRange                       = 1.5; // Maximum vdda_v level (V)
   parameter real vdda_v_LoRange                       = 1.0;  // Minimum vdda_v level (V)        

   parameter real dv   = 1n;   // Safety margin for voltage threshold crossing     (V)

   reg     vdda_v_flag;

   initial begin
       vdda_v_flag     = 1'b0;
   end

   integer output_file;  

   initial begin
       output_file = $fopen("log_file.txt");
   end  

   always @(   above(V(vdda_v)-(vdda_v_LoRange)) or above((vdda_v_HiRange)-V(vdda_v)) or                // vdda_v rises above the low threshold or falls below the high threshold
                   above((vdda_v_LoRange-dv)-V(vdda_v)) or above(V(vdda_v)-(vdda_v_HiRange+dv))          // vdda_v rises above the high threshold or falls below the low threshold  
   ) begin
                 
       if (    (V(vdda_v)>=vdda_v_LoRange) && (V(vdda_v)<=vdda_v_HiRange)    ) begin
           vdda_v_state    = 1'b1;
           vdda_v_flag     = 1'b1;
           
       end else begin
           vdda_v_state    = 1'b0;
           if (vdda_v_flag==1'b1) begin
               $fstrobe(output_file, "WARNING: V(vdda_v)=%gV is exceeding the defined safety ranges at time=%gus\n", V(vdda_v), $realtime);    
           end
       end                      
   end  


previous code is working fine. Now I want to check the value of vdda_v_flag "at the end of simulation".


I want to use this code:

   always @(final_step) begin
       if (vdda_v_flag==1'b0) begin      
           $fstrobe(output_file, "WARNING HIGH SEVERITY: V(vdda_v) was outside the defined voltage ranges during the complete simulation");
       end
   end    


The code compiles without errors.

But when I run the simulation errors are encounted:


Error found by spectre during circuit read-in.
   ERROR (VACOMP-1974):
       ".../verilog.vams",
       line 231: Unsupported analog event in digital context.
   ERROR (VACOMP-1816): Exiting AHDL compilation.
ncsim: *F,INTERR: INTERNAL EXCEPTION
Observed simulation time : 0 FS + 0


So my question is: how can I check in the digital context the final value of a signal at the end of simulation in verilogams???

Thank you!