Hi have the following verilog-a block for a random number generator:

--

// VerilogA for Example, RdnGen, veriloga

`include "constants.vams"
`include "disciplines.vams"

module RdnGen(out);

output out;
electrical out;

integer randn;
integer sign;

analog begin

randn = $random %60;
sign = (randn < 0) ? 1:-1;

@(initial_step)

$strobe

("Rand\t\t",randn,
"\n", "Sign\t\t", sign,
"\n\n\n\n\n");

end
endmodule
~            

--

I don't understand why every single time I run this code the "randomly" generated number is always the same.

Any hints ?

Thank you,

Thank you very much for your answer,

However, we've observed that for IC5.1 that is not the case, as for each DC op point simulation we obtain a different randomly generated number. This issue has appeared in the virtuoso 6.1.5 version.

As a secondary question, what would be an alternative then to obtain a randomly generated sign (+ or -) for a signal that would be used as a DC offset for an amplifier model ?

Regards,

Lucho.