Dave Rittel
New Member
Offline
Posts: 1
|
Hello All,
I have simulated the phase noise of frequency dividers in the past numerous times using the method defined in Chapter 6 of "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers" by Ken Kundert.
I believe that I could use the same method to run the phase noise on a frequency multiplier, but I'm having trouble finding a reference. Does anybody have experience running phase noise simulations on frequency multipliers or know of a reference?
I'm basically following the directions as described in the frequency divider chapter (Chapter 6) with a couple changes. I'm doubling a 100MHz input to a 200MHz output. The beat frequency is 100MHz, and I'm doing a relative sweeptype in pnoise and looking at the noise at the 2nd harmonic. Other than that, I believe the method is the same. I define a zero crossing in pnoise and look at the noise there. From there, I calculate the phase noise from the output frequency, the slew rate at the zero crossing, and the zero-crossing noise.
Thanks in advance for your help, Dave
|