Dear Members,

well it's been a long time since my last post and since I was using verilogams.

Now I have a to do a simple model but somehow I cannot figure out what is wrong as the code is not working as I expect it to do. Hopefully you can help me out to find the error.

The basic concept is 1bit dac i.e. the input is a digital signal (1bit) that must be converted into an analog signal.

I want to use "Digital Access on Demand", in more detail "Analog Sensitivity to Digital Events"

As a reference I am using the book "The Designer's Guide to VerilogAMS" by Kenneth S. Kundert", section 3.2.2, page 116, "Analog Sensitivity to Digital Events", Listing 11.

Here is my code:

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns/1ps

module dac_1bit_model1 ( out_ana, in_dig);
   
   inout out_ana;
   electrical out_ana;
   
   inout in_dig;
   logic in_dig;
   
   real value_ana;
       
   analog begin
   
       @(posedge in_dig) value_ana = 1.2;
       @(negedge in_dig) value_ana = 0.0;
       @(initial_step) value_ana = (in_dig ? 1.2 : 0.0);
       
       V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n);      
   
   end
       
endmodule


Well, for me the code looks ok.

As you can see from pict1 the sensitivity to the events in signal "in_dig" is not working properly because the real variable "value_ana" is corrupt and therefore the transition to V(out_ana) is also corrupt.

I was thinking of possible reasons:

1. I need to include following lines inside the analog block in order to increase the accuracy:

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns/1ps

module dac_1bit_model1 ( out_ana, in_dig);
   
   inout out_ana;
   electrical out_ana;
   
   inout in_dig;
   logic in_dig;
   
   real value_ana;
   
   analog begin
   
      @(posedge in_dig)
             ;

       @(negedge in_dig)
             ;
   
       @(posedge in_dig) value_ana = 1.2;
       @(negedge in_dig) value_ana = 0.0;
       @(initial_step) value_ana = (in_dig ? 1.2 : 0.0);
       
       V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n);

   end
       
endmodule

the problem is that I have tried this already and I see no difference in the results.

2. I also tried out this code:

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns/1ps

module dac_1bit_model1 ( out_ana, in_dig);
   
   inout out_ana;
   electrical out_ana;
   
   inout in_dig;
   logic in_dig;
   
   real value_ana;
   
   
   analog begin
   
   
       @(posedge in_dig)
             $discontinuity(0);

       @(negedge in_dig)
             $discontinuity(0);
   
       @(posedge in_dig) value_ana = 1.2;
       @(negedge in_dig) value_ana = 0.0;
       @(initial_step) value_ana = (in_dig ? 1.2 : 0.0);
       
       V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n);
       
   
   end
       
endmodule

but results are identical.



3. Accuracy Settings, may be I have to change some tool accuracy settings, but I think this is not the problem. So here I have not done any attempt.
   
   
I am very happy about your suggestions, comments.

Regards!
Douglas

Zorro,
model2 is correct and working as expected because transition filter should have discrete (and not continuous as in model1) input.
- B O E

Hi Zorro,
I just tested it. model2 works. Maybe you're using an old/buggy tool version?
- B O E

Hi All,

I am using cadence 6.1.5 so I do not think that the problem is because the software is outdated.  :(

Zorro,
   Please disregard BOE's suggestion that you should use your model2. I would not expect that model to work well. However, I would think your model1, though perhaps overly complicated, should work well. I am surprised it is not, and I believe it is something that you should discuss with your simulator company. You may be stumbling over a bug. Having said that, there are ways you can improve your model and perhaps overcome the problem you are having. I would suggest using something like:
Code:

module dac_1bit_model (out_ana, in_dig);
   output out_ana; electrical out_ana;
   input in_dig; logic in_dig;

   analog begin
	 @(posedge in_dig or negedge in_dig)
		 ;

	 V(out_ana) <+ transition(in_dig ? 1.2 : 0.0, 0, 1u, 1u);
   end
endmodule 

Somethings to notice about this implementation:

• The @(...) controls the timestep in the analog simulator, forcing it to place time points at changes in the digital input. In this way, no changes in the digital input should be missed.
• The output is produced by a transition function, meaning that the transitions will be well controlled. (This seems to be the problem you are having, your transitions are not well controlled.)
• The output is computed on every analog timestep using "in_dig ? 1.2 : 0.0", making the model more robust (no need to worry about initializing the state).
• The digital value is tested using the ?: operator, eliminating any chance that an X value will get into the analog output signal.
• I increased the transition time to 1us, which seems much more reasonable for the simulation you are running (using too small of a transition time can waste considerable simulation time).

-Ken

Hi Ken,

I have spent hours trying different approaches and combinations without success.

I am sorry to say that your suggested code is also not working.

It seems that there must be a bug in the software. I will contact CAD Support tomorrow so that they can have a look.

I will use your suggested code to show the error.

Attached some pictures and below the codes that I am using.



clk_gen

`include "constants.vams"
`include "disciplines.vams"
`timescale 1us/1ps

module clk_gen(clk);

   output clk;
   reg clk;
   
   parameter real period = 4;  // clock period (us)
   parameter real td = 0.0;    // delay (us)                                      
                                       
   initial begin  
       clk = 0;
       #(td) clk = ~clk;
       forever begin
           #(period/2) clk = ~clk;
       end
   end  

endmodule


dac_1bit_model8

`include "constants.vams"
`include "disciplines.vams"
`timescale 1us/1ps

module dac_1bit_model8 ( out, in);

   inout out;
   electrical out;
   
   inout in;
   logic in;
   
   real value;
   
   analog begin
   
       @(posedge in or negedge in)
           ;
                     
       V(out) <+ transition(in ? 1.2 : 0.0, 0.0, 1n, 1n);

   end

endmodule



Best Regards!
Douglas

Did you ever try setting the transition time to something not so extreme?

-Ken

There are a couple of lessons to be taken from this.

First, you should not be using skip count. One should only use skip count if the size of the simulation data file is problematic, and when you use it and you get unexpected results, you should always place it high among the list of likely perpetrators. There is a reason why the simulator computes all those time points, and ignoring half of them or more is a dubious practice that should only be used if you are desperate.

Second, you should always generate a simple example and give the complete example on this forum if you want people to help you. If you had given the model and the netlist, you would have gotten an answer to your problem right away.

Lastly, and this is for Cadence, not you, Spectre should always output the break points regardless of skip count. This is the "bug" I mentioned in my previous message. Perhaps you can pass this suggestion/bug report back to whomever you were talking to at Cadence.

-Ken