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Simulating Verilog-A and Verilog-D together (Read 2390 times)

mowiehowie Junior Member Offline Posts: 26	Simulating Verilog-A and Verilog-D together Feb 28^th, 2014, 8:49am Hello, Anyone could help me to find out how can I simulate Verilog-A and Verilog-D modules instantiated in the same schematic when using Virtuoso ADE ? Any tutorials ? Thanks,
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Andrew Beckett

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Re: Simulating Verilog-A and Verilog-D together
Reply #1 - Feb 28^th, 2014, 9:40am

These are in the documentation. If using IC615 or IC616 (say), in the CIW, you can do Help->Virtuoso Documentation, and then expand "AMS Environment" and then "Virtuoso AMS Designer Environment Tutorials".

The tutorial databases are at <ICinstDir>/tools/dfII/samples/tutorials/AMS - there are a number of gzipped tar files in there and a PDF. In particular AMSDInADE.tar.gz is a good place to start.

The tutorials are in the same place in IC5141 too.

Regards,

Andrew.

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