Hi Everyone, i'm having trouble at the moment as i am verifying a top level which has multiple supplies. I'm using supply sensitive connect modules and my functional models all have supply sensitive statements in there IO list. My top level testbench is text based VerilogAMS.

My problem is when it comes to doing mixed level simulations. When i swap one of my instantiated models for the schematic equivalent, i have errors with the supply sensitive connect modules.

All the 'solutions' i've found involve changes parameters of the pins or of the block itself by clicking on visual items etc on the schematic. Obviously i can't do that in a text based testench.

I've blindly tried adding the same supply sensitive statements in my testbench but since there are no inputs/outputs in the testbench, it doesn't work.

Does anyone have any ideas or can they point me in the direction of where i could find the info?

Thanks in Advance.

Hi Andrew, thanks for the reply. Apologies for the delay, i didn't realise you had replied to this topic ( i thought i would get an email notification!)

I'm still having no luck with this situation. I've created a testcase library which i forwarded to our EDA/CAD guys but i still haven't had any resolution.

I apologise in advance for the size of this post but i will try and detail the scenario as much as possible.

I have a top level testbench called tb_supply_sensitive_testcase which has the following views:
 verilogams - the verilogams text based tesbench (shown below)
 schematic - the schematic equivalent of the vams testbench
 config_sch - the config view where everything is in schematic
 config_vamstb_schdut - config where tb is vams, instantiated blocks are schematic
 config_vamstb_vamsdut - config where everything is vams
 ams_state_config_sch - simulation state for config_sch
 ams_state_vamstb_schdut - simulation state for vamstb/sch blocks
 ams_state_vamstb_vamsdut - state for everything in vams

I then have 4 cells:
 logic_cell_1_5v - an AND gate from a 7v library
 logic_cell_2_1v8 - an AND gate from a 1.8v library
 LS_down_5v_to_1v8 - a "Down" Levelshifter (a 7v buffer)
 LS_up_1v8_to_5v - an "Up" Levelshifter
All of which have 3 views:
 symbol
 schematic
 verilogams

Where the verilogams view is a direct representation of the schematic but they include supply sensitivity statements on the IOs.

The verilogams testbench is as follows:
Code:

`include "constants.vams"
`include "disciplines.vams"

`timescale 1s/1ns

module tb_supply_sensitive_testcase ( );

electrical tb_VDD_5v;
electrical tb_VDD_1v8;
electrical tb_VSS;

reg tb_in1;
reg tb_in2;
reg tb_in_logic_2;
reg tb_por;

wire tb_out;
wire tb_out_logic_1;
wire tb_out_dn;
wire tb_out_logic_2;

real v_VDD_1v8_r = 1.8;
real v_VDD_5v_r = 5;
real transition_time = 100n;


initial begin
  tb_in1 = 1'b0;
  tb_in2 = 1'b0;
  tb_in_logic_2 = 1'b0;
  tb_por = 1'b0;

  $display("INFO: Simulation begins");
  #(transition_time);

  tb_in1 = 1'b1;
  tb_in_logic_2 = 1'b1;
  #(10u);
  tb_in2 = 1'b1;
  #(10u);
  tb_in1 = 1'b0;
  #(10u);
  tb_in2 = 1'b0;
  #(10u);
  tb_in_logic_2 = 1'b0;
  #(10u);
  
  $display("INFO: Simulation ends");
  $finish;
  
end

analog begin
  V(tb_VDD_1v8) <+ transition(v_VDD_1v8_r, 0, transition_time);
  V(tb_VDD_5v) <+ transition(v_VDD_5v_r, 0, transition_time);
  V(tb_VSS) <+ 0;
end

logic_cell_1_5v I_logic_1 (
  .in1(tb_in1),
  .in2(tb_in2),
  .out(tb_out_logic_1),
  .VDD(tb_VDD_5v),
  .VSS(tb_VSS)
);
LS_down_5v_to_1v8 I_levshift_dn (
  .in(tb_out_logic_1),
  .out(tb_out_dn),
  .VDD(tb_VDD_1v8),
  .VSS(tb_VSS)
);
logic_cell_2_1v8 I_logic_2 (
  .in1(tb_out_dn),
  .in2(tb_in_logic_2),
  .out(tb_out_logic_2),
  .VDD(tb_VDD_1v8),
  .VSS(tb_VSS)
);
LS_up_1v8_to_5v I_levshift_up (
  .OUT(tb_out),
  .nOUT(),
  .POR(tb_por),
  .IN(tb_out_logic_2),
  .V1p8(tb_VDD_1v8),
  .V7D(tb_VDD_5v),
  .VSS(tb_VSS)
);

endmodule

 

And the following code is the verilogams views of the 4 cells instantiated in the testbench.

Code:

`include "constants.vams"
`include "disciplines.vams"

module logic_cell_1_5v ( out, VDD, VSS, in1, in2 );

  input VDD;
  input  (* integer supplySensitivity = "VDD";
            integer groundSensitivity = "VSS"; *) in2;
  input  (* integer supplySensitivity = "VDD";
            integer groundSensitivity = "VSS"; *) in1;
  input  (* integer supplySensitivity = "VDD";
            integer groundSensitivity = "VSS"; *) VSS;
  output  (* integer supplySensitivity = "VDD";
            integer groundSensitivity = "VSS"; *) out;

  electrical VDD;
  electrical VSS;

  wire out;

  assign out = in1 && in2;
endmodule

 

Code:

`include "constants.vams"
`include "disciplines.vams"

module logic_cell_2_1v8 ( out, VDD, VSS, in1, in2 );

  input VDD;
  input (* integer supplySensitivity = "VDD";
           integer groundSensitivity = "VSS"; *) in2;
  input (* integer supplySensitivity = "VDD";
           integer groundSensitivity = "VSS"; *) in1;
  input VSS;
  output (* integer supplySensitivity = "VDD";
           integer groundSensitivity = "VSS"; *) out;

  electrical VDD;
  electrical VSS;

assign out = in1 && in2;

endmodule

 

Code:

`include "constants.vams"
`include "disciplines.vams"

module LS_down_5v_to_1v8 ( out, VDD, VSS, in );

  input VDD;
  input VSS;
  input (* integer supplySensitivity = "VDD";
           integer groundSensitivity = "VSS"; *) in;
  output (* integer supplySensitivity = "VDD";
           integer groundSensitivity = "VSS"; *) out;

  electrical VDD;
  electrical VSS;

  wire out;
  assign out = in;
endmodule

 

Code:

`include "constants.vams"
`include "disciplines.vams"

module LS_up_1v8_to_5v ( OUT, nOUT, POR, IN, V1p8, V7D, VSS );

  output (* integer supplySensitivity = "V7D";
            integer groundSensitivity = "VSS"; *) nOUT;
  input V7D;
  input (* integer supplySensitivity = "V1p8";
            integer groundSensitivity = "VSS"; *) IN;
  input (* integer supplySensitivity = "V7D";
            integer groundSensitivity = "VSS"; *) POR;
  output (* integer supplySensitivity = "V7D";
            integer groundSensitivity = "VSS"; *) OUT;
  input VSS;
  input V1p8;

  electrical V7D;
  electrical VSS;
  electrical V1p8;

  assign OUT = IN;
endmodule

 

Obviously i can't give the schematics but as i said above they are direct representations of the verilogams views.

Oops run out of characters, i'll follow up in a second post. Thanks.

So to continue on from the previous post...

I have a testbench with 2 power supplies; 5v and 1.8v. I also have 4 instantiated cells which use the 2 power supplies. I'm trying to simulate with supply sensitive connect modules with Virtuoso ADE L, simulator set to AMS, and the netlister set to use the OSS based netlister with irun.

I now have 2 scenarios:
1. Everything in verilogams - Everything works, the supply sensitivity statements in the models take care of the connect modules and we are all ok!
2. Trying to set any or all of the instantiated blocks to schematic. I get error messages that the supply sensitivity is not set for pins on the blocks etc. Error messages similar to:

Code:

reg tb_in1;
         |
ncelab: *E,AMSSOM (/data/GEN6_OA_DS/sync/users/a0413320/Latest/cds/supply_sensitive_testcase/tb_supply_sensitive_testcase/verilogams/verilog.vams,16|9): Ports connecting to net 'tb_supply_sensitive_testcase.tb_in1' miss override value of sensitivity attribute 'supplySensitivity'. Add it and run again.
 electrical (* integer supplySensitivity = "cds_globals.\\vdd! " ; *) \vdd! ;
                                                               |
 

The above error message is from the ams_state_vamstb_schdut.

I know that i need to set supply sensitivity for the instantiated blocks. However, i'm not sure how.

Any help would be greatly appreciated!

Thank you.

Amblik wrote on Jan 21^st, 2014, 4:01am:
It forces the internal nodes to digital domain so CMs will be added at the terminals, where you have sensitivity attributes. I'm not sure if e.g. Code:

 assign out=in; 

creates any CMs if in & out have the same discipline.
Oh, and did that help?
- B O E

boe wrote on Jan 21^st, 2014, 4:36am:


Adding properties to the schematic ports is essentially what i'm trying to do. However, i'm not sure how to achieve that.

Any thoughts? Thanks.

boe wrote on Jan 21^st, 2014, 4:58am:


Well now!! This appears to work!

There is a "but" though. (And it's quite a big but!). It's quite labor intensive! There's no way i'd be able to go through every pin in a top level IC and set the attributes. Is there a quicker way to do this?

We're so close!

Also, when i edit the pin properties for schematic/symbol and then check and save, i get warnings that the pins don't match the verilogams view? Do you have an idea of why it might be saying that? How to get rid of the warnings?

Thank you very much!

boe wrote on Jan 21^st, 2014, 6:05am:


To be honest, the more i think about it, i might have to make it stimulus based to get round this.

I didn't really want to do that. (although i'm not really sure WHY i didnt really want to do that! If it makes any sense!

Thanks again for your help!