Hi all,


first off I am new to Veriloga. I am trying to model a digital control loop, but I am storing variables as "real" type. I would like to constrain the resolution of my signals to a certain number of bits to make the system more realistic. Is there any way to do this?

I'm thinking I need the simplest possible ADC function. What I've come up with is :

var = var - var % resolution;

where var is the number I want to constrain, and % is the modulus function. Not sure if this works or if there's a better way though.


thanks,
Aaron

Thanks!