The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
May 18th, 2024, 8:48pm
Pages: 1
Send Topic Print
CMOS Self-Biased Cascode Power Amplifier (Read 9713 times)
baab
Senior Member
****
Offline



Posts: 178
EA
CMOS Self-Biased Cascode Power Amplifier
Sep 08th, 2013, 3:40am
 
Hi,
I am studying the article "A 2.4-GHz 0.18-um CMOS Self-Biased Cascode Power Amplifier" (attached). Here are what I am confused. Please help. Thank you.

Back to top
 

Class_1_PA_text.JPG
View Profile   IP Logged
baab
Senior Member
****
Offline



Posts: 178
EA
Re: CMOS Self-Biased Cascode Power Amplifier
Reply #1 - Sep 8th, 2013, 3:41am
 
Second image.
Back to top
 

Class_I_PA_modified.JPG
View Profile   IP Logged
baab
Senior Member
****
Offline



Posts: 178
EA
Re: CMOS Self-Biased Cascode Power Amplifier
Reply #2 - Sep 8th, 2013, 3:46am
 
The article:
Back to top
 
View Profile   IP Logged
raja.cedt
Senior Fellow
******
Offline



Posts: 1516
Germany
Re: CMOS Self-Biased Cascode Power Amplifier
Reply #3 - Sep 8th, 2013, 5:12am
 
Hello,
I am not an RF expert, i will try to ans what i know.

1. Dc choke you can't integrate on chip, in principle RC or LC works fine.

2. min value of Cascode gate voltage should be equal to Vth+2*vov and max below Vo+vth, since there is an inductor at the o/p DC operating point is around vdd, so Vdd at gate make scene.

3. I guess this is to create 50 Ohm or required real input impedance with out having noisy resister at the input...

Thanks,
Raj.
Back to top
 
 
View Profile WWW raja.sekhar86   IP Logged
baab
Senior Member
****
Offline



Posts: 178
EA
Re: CMOS Self-Biased Cascode Power Amplifier
Reply #4 - Sep 8th, 2013, 5:36am
 
Thank you, Raj.
Quote:
1. Dc choke you can't integrate on chip, in principle RC or LC works fine.

I am not sure but I usually see that RF choke is used in chips.
But inductor will be better than resistor? I think if we use resistor, there will be some energy dissipated thermally. If inductor is used no RF signal flows through it and no losses but when the resistor Rg is used RF signal will flow through it to ground and causes losses.
Quote:
2. min value of Cascode gate voltage should be equal to Vth+2*vov and max below Vo+vth, since there is an inductor at the o/p DC operating point is around vdd, so Vdd at gate make scene.

Vth + 2Vov < Vbias < Vo + Vth
I have read cascode configuration and this is metioned too. But how can you know the values of Vov and Vo?  :-[ Quote:
3. I guess this is to create 50 Ohm or required real input impedance with out having noisy resister at the input...

Sorry, is this the answer for Q3?
Back to top
 
 
View Profile   IP Logged
baab
Senior Member
****
Offline



Posts: 178
EA
Re: CMOS Self-Biased Cascode Power Amplifier
Reply #5 - Sep 8th, 2013, 8:11am
 
I have seen this conventional cascode configuration amplifier. Please help me with this question too.
Back to top
 

Cascode_1_9modified.JPG
View Profile   IP Logged
raja.cedt
Senior Fellow
******
Offline



Posts: 1516
Germany
Re: CMOS Self-Biased Cascode Power Amplifier
Reply #6 - Sep 8th, 2013, 9:39am
 
Lg1,Lg2 are bondwire inductance (Just because they are after the pad)
Rg1,Rg2 are biasing resisters.
Ls1 also bondwire inductance but it will be used to create real Zin
Back to top
 
 
View Profile WWW raja.sekhar86   IP Logged
aaron_do
Senior Fellow
******
Offline



Posts: 1398

Re: CMOS Self-Biased Cascode Power Amplifier
Reply #7 - Sep 8th, 2013, 6:03pm
 
Hi,


Ls1 is a bond-wire inductance which changes the real part of the input resistance, but I wonder if it is deliberately added, and not just part of the model. It can help to improve the linearity, but there are a few tradeoffs.

1. Stability may be degraded due to feedback.

2. Maximum output power is potentially lowered. Check the voltage swing at the drain and source. If they are out-of-phase, then your maximum output power is lowered.

3. Maximum efficiency may drop. For a given supply voltage, if the swing at the output is reduced, the peak efficiency may also drop.

4. Maximum power gain is reduced. This follows from the drop in input impedance, and the drop in Gm. You might want to check this, but just intuitively I think its true.

As far as I know, Ls1 is not typically added in a power amplifier (especially the output stage), but is extremely common for LNA design.

Second issue. As Raja.cedt said, Rg1 and Rg2 do not cause any loss as long as they are large enough. RF chokes are very large and aren't really implementable on chip. However, if ACPR or your spectrum mask requirements are stringent, then you may find the use of biasing resistors problematic. I can't remember the exact theory, but I believe if you do a volterra series analysis of a nonlinear impedance, you will find that the "baseband impedance" (actually any harmonic impedance I think) can affect the intermodulation performance. Using an RF choke allows you to make the baseband impedance equal to zero. Transformer matching does the same thing. It really depends on your application, but you may want to bear it in mind.


regards,
Aaron
Back to top
 
 

there is no energy in matter other than that received from the environment - Nikola Tesla
View Profile   IP Logged
tm123
Community Member
***
Offline



Posts: 67
Chicago, IL
Re: CMOS Self-Biased Cascode Power Amplifier
Reply #8 - Sep 9th, 2013, 10:18am
 
My comments:

1) The transistors need to be biased in saturation, and biasing the cascode gate at VDD provides maximum headroom to M1.  This is important for linearity especially with voltage swing at node D1.  Ideal analysis usually assumes that the Zin of the cascode (looking in to the source of M2) is zero but it is really 1/gm of M2 which can be quite large in MOS depending on the bias current and M2 W/L

2) RF choke inductor is not practical to implement on chip because it is very area inefficient.  A large resistor is sufficient to provide a large impedance at RF.  Something like 10K-20K ohm should do it.

3) In a single ended design like this you are stuck with bondwire inductance between the source of M1 and the actual ground.  You can use this inductance to your advantage since inductance at the source makes the small signal input impedance of the amplifier look like a purely real impedance, i.e. resistance (this is a good derivation to do and have for reference).  If designed properly you can obtain a reasonable impedance match without using a shunt resistor that causes loss (not good if you care about noise figure).  The inductance also provides some degeneration which will improve linearity.

I am not sure what your ultimate goal is but it has been my experience that trying to learn design from IEEE papers is extremely difficult because the authors assume you have certain basic knowledge and often times leave out important design details.  If you are trying to learn about design I suggest using textbooks by authors such as Thomas Lee and Behzad Razavi since they start from very basic principles and build up to more complex topics.
Back to top
 
 
View Profile   IP Logged
baab
Senior Member
****
Offline



Posts: 178
EA
Re: CMOS Self-Biased Cascode Power Amplifier
Reply #9 - Sep 19th, 2013, 12:32am
 
Thank you, aaron_do and tm123. I really appreciate your helps.
Aaron:
Quote:
Ls1 is a bond-wire inductance which changes the real part of the input resistance, but I wonder if it is deliberately added, and not just part of the model.

With input resistance, do you mean output resistance of the previous stage (usually 50 or 75 ohms)?
If I understand you correctly, L1 is also added to help in input matching network. It will be used to compensate Cgs, Cgd and other capacitive components.
Quote:
It can help to improve the linearity, but there are a few tradeoffs.

Could you tell me how it improve the linearity? I don't want to take you a lot of time, so please give me a link or some keywords therefore, I can search it myself. English is not my native language and I feel a bit difficult in finding keywords.
Quote:
1. Stability may be degraded due to feedback.

I don't know why stability is degraded. I think it should be upgraded because negative feedback. However, power gain is decreased due to the feedback.
Quote:
2. Maximum output power is potentially lowered. Check the voltage swing at the drain and source. If they are out-of-phase, then your maximum output power is lowered.

Is it because when they are out of phase => Vds > 0 and there is part of power dissipated in MOSFET?
Quote:
3. Maximum efficiency may drop. For a given supply voltage, if the swing at the output is reduced, the peak efficiency may also drop.

Yes, I see it. Smiley
Quote:
. Maximum power gain is reduced. This follows from the drop in input impedance, and the drop in Gm. You might want to check this, but just intuitively I think its true.

Yeah.
Quote:
As far as I know, Ls1 is not typically added in a power amplifier (especially the output stage), but is extremely common for LNA design.

I guess its role is to reduce noise figure, NF.
Quote:
Second issue. As Raja.cedt said, Rg1 and Rg2 do not cause any loss as long as they are large enough. RF chokes are very large and aren't really implementable on chip. However, if ACPR or your spectrum mask requirements are stringent, then you may find the use of biasing resistors problematic. I can't remember the exact theory, but I believe if you do a volterra series analysis of a nonlinear impedance, you will find that the "baseband impedance" (actually any harmonic impedance I think) can affect the intermodulation performance. Using an RF choke allows you to make the baseband impedance equal to zero. Transformer matching does the same thing. It really depends on your application, but you may want to bear it in mind.

I don't get this. For Rg1, Rg2 to be bias resistor, it has to be as small as possible to reduce power losses. However, with RF signal, to reduce losses of RF signal, Rg1, Rg2 has to be as big as possible. Then there is a trade-off here.
But you said it causes no losses. I am really confused about this. Because resistances, I think there are always losses in these components.
Back to top
 
 
View Profile   IP Logged
aaron_do
Senior Fellow
******
Offline



Posts: 1398

Re: CMOS Self-Biased Cascode Power Amplifier
Reply #10 - Sep 19th, 2013, 1:28am
 
Hi baab,

Quote:
With input resistance, do you mean output resistance of the previous stage (usually 50 or 75 ohms)?
If I understand you correctly, L1 is also added to help in input matching network. It will be used to compensate Cgs, Cgd and other capacitive components.


No, I mean the input resistance of the PA (not the previous stage). You can do some reading on the "inductive degeneration" technique for LNA design to understand what I mean. It is a feedback technique which is used to add a real part to the input impedance. Without it, the input impedance of would be mostly capacitive. It may partially compensate Cgs or Cgd, but that is not its main purpose for input matching.

Quote:
Could you tell me how it improve the linearity?


Its been a while, so I can't think of any references, but Ls1 is a source-degeneration inductor. It provides negative feedback and therefore should improve the linearity. However, I don't think it provides much negative feedback, and so it probably doesn't improve linearity very much.

Quote:
I don't know why stability is degraded. I think it should be upgraded because negative feedback. However, power gain is decreased due to the feedback.


Instability is caused by unwanted positive feedback. Ls1 may provide positive feedback at some frequency that you didn't pay enough attention to. It completely depends on your design. When your design is at a very high frequency, or high power, you will see all kinds of unwanted feedback paths causing problems, and a simpler design is easier to manage. I'm not sure if stability is ever "upgraded" due to negative feedback.

Quote:
Is it because when they are out of phase => Vds > 0 and there is part of power dissipated in MOSFET?


Its not directly because of any power dissipated in the transistor, although that might factor in too. Maximum output power depends on the maximum swing that can be generated at the output. The minimum that the drain voltage can swing is equal to the source voltage + the drop across the transistor. This will in turn determine the maximum swing. So you ideally don't want your source voltage swinging out-of-phase wrt the drain voltage.

Quote:
I guess its role is to reduce noise figure, NF.


Yes that's true for an LNA, but its not very important for a PA.

Quote:
I don't get this. For Rg1, Rg2 to be bias resistor, it has to be as small as possible to reduce power losses.


You seem to have a misunderstanding here which is quite common. Rg1 and Rg2 are in parallel with the signal path. Ideally you don't want any power from your main signal to pass through the resistors. Therefore, the larger they are, the less the loss. It has nothing to do with RF. Just like an insulator surrounding any wiring. The insulator is in parallel with the signal path, and so you want it to have as high a resistance as possible. When I said no losses I meant negligible losses.

That said, the issue I was referring to (about the intermodulation performance) is a bit deeper, so maybe you should just ignore it for now.


hope it helps,
Aaron
Back to top
 
 

there is no energy in matter other than that received from the environment - Nikola Tesla
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.