I want to design a simple resistor in verilog-A i used following verilog code
//------------------------------------------------------------------------------
------------------
`include "constants.vams"
`include "disciplines.vams"
module Table_NL_Resistor(a,b);
inout a;
inout b;
electrical a,b;
parameter real k = 0 from [0:inf);
analog begin
     V(a,b) <+ k*$table_model(I(a,b),"sample.dat");
end
endmodule
//------------------------------------------------------------------------------
------------------

i tried to simulate above model in cadence spectre it works fine when i connect current source in series with above resistor. Voltage and current Waveform appear properly after simulation


but while simulating using Voltage source in series with above element no Waveform shows up at the output.


how do i overcome above limitation ...?

how can i model such elements in verilogA using look up table based approach ..?


plz Suggest

Thank You,
Ganesh