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macaren

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how to decrease the rs/rd noised reported by the cadence noise summary?
Jul 20^th, 2012, 6:41pm

the chip is switch-cap circuit. and using the cadence spectreRF do pnoise analaysis. the noise summary shows that there are three switchs contribute above 70% of the total noise. the noise type are rs and rd. does thes make sense? what is the rs/rd noise? how to fix this?

the switch is paralleal of the PMOS and NMOS. both size is 2.2u/0.8u.

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Dan Clement Community Member Offline Posts: 95 Salt Lake City, Utah, USA	Re: how to decrease the rs/rd noised reported by the cadence noise summary? Reply #1 - Jul 20^th, 2012, 7:42pm Are these ESD transistors? If so then rs and rd could make sense. I would make sure your settling time is good. Hopefully you have looked into that before running the sim. Without more specifics I'm not sure we can offer much more insight.
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macaren New Member Offline Posts: 6	Re: how to decrease the rs/rd noised reported by the cadence noise summary? Reply #2 - Jul 21^st, 2012, 12:24am the attached picture is the circuit and the pnoise noise summary. the switchs named I99/I102/I107 are all labeled in the picture. thanks in advance.
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Dan Clement Community Member Offline Posts: 95 Salt Lake City, Utah, USA	Re: how to decrease the rs/rd noised reported by the cadence noise summary? Reply #3 - Jul 22^nd, 2012, 7:38am Im not really sure what to think about this. Have you looked into the modeling information in the pdk? Maybe it has something to do with how they implemented the model. Sorry I don't have much to offer.
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BackerShu

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Re: how to decrease the rs/rd noised reported by the cadence noise summary?
Reply #4 - Jul 24^th, 2012, 3:26pm

To my understand, the noise contribution of this SC circuit, in holding phase, would mainly be the noise from OTA, which will normall show as "id" noise; yet, the summary shows that the �top 6 noise contributors are not related to OTA at all!

Here are somethings I am curious:

Are you using ideal OTA here?

Did you make sure the Pnoise simulation results meet with the AC noise simulation results in a particular clocking phase?

Total integrated noise seems to be big. What is the noise bandwidth? Does this meet your requirement?

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Thanks and Regards!
BackerShu

https://www.linkedin.com/pub/shu-guanghua/26/b72/711

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macaren New Member Offline Posts: 6	Re: how to decrease the rs/rd noised reported by the cadence noise summary? Reply #5 - Jul 28^th, 2012, 6:25pm thanks to BackerShu yes. the OTA is real circuit. due to the first use of the PNOISE. I am not sure it is ok. the below picture one is for the noise analysis at each phase. and the other is the pnoise result.
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macaren New Member Offline Posts: 6	Re: how to decrease the rs/rd noised reported by the cadence noise summary? Reply #6 - Jul 28^th, 2012, 6:26pm this is the noise analaysis at each two phase. [img][/img]
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macaren

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Re: how to decrease the rs/rd noised reported by the cadence noise summary?
Reply #7 - Jul 28^th, 2012, 6:42pm

Due to the CDS is added to the circuit, the noise performance is improved at low frequency(about several tens). but above tens of Hz. The pnoise result seems strange. take 1KHz as example. pnoise result is 401nv/sqrt(Hz). noise analysis at each phase is about 71nv/sqrt(Hz). The pnoise result is six times of the seperate phase.
Does this make sense? (noise folding?)

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BackerShu

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Re: how to decrease the rs/rd noised reported by the cadence noise summary?
Reply #8 - Jul 30^th, 2012, 3:46pm

Two questions:

1. What is the main noise contributor now? Does it becomes the OTA?
2. There is a clear flatten region in Pnoise results, which doesn't seem right. I am not sure whether CDS would cause this noise profile. Probably not.

One thing you need to make sure is when using Pnoise to simulate the noise in SC circuit, check the sampled output signal. You may want to take a look at this paper.
http://www.designers-guide.org/Analysis/sc-filters.pdf

Hope this helps.

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Thanks and Regards!
BackerShu

https://www.linkedin.com/pub/shu-guanghua/26/b72/711

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BackerShu

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Re: how to decrease the rs/rd noised reported by the cadence noise summary?
Reply #9 - Jul 31^st, 2012, 1:29am

Hello macaren,

I checked some paper about CDS. It can suppress 1/f noise to some extent, but cannot vanish the low frequency noise since sampling behavior will alias high frequency back to low frequency; Also, the white noise power is doubled since correlated double sampling essentially makes two measurements of the uncorrelated (white) signal.

You may want to check the following paper:

[1] J. M. Pimbley; and G.J Michon, �The output power spectrum produced by correlated double sampling,� IEEE Transactions on Circuits and Systems, vol. 38, no. 9, pp. 1086�1090, 1991.

Hope this helps.

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Thanks and Regards!
BackerShu

https://www.linkedin.com/pub/shu-guanghua/26/b72/711

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macaren

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Re: how to decrease the rs/rd noised reported by the cadence noise summary?
Reply #10 - Aug 2^nd, 2012, 7:18pm

yes, I have confirmed that this pnoise result is right, because of the noise folding effect , the noise at high frequency is aliased to the low frequecy we cared. so the pnoise resut is several times of the noise at each seperate phase. the next action is what facts affect the noise folding...

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neoflash

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Re: how to decrease the rs/rd noised reported by the cadence noise summary?
Reply #11 - Dec 8^th, 2015, 10:04pm

Did you figure out why rd/rs is the major noise source instead of id?

I happened to see similar thing in one of my design. Still haven't figured out why?

macaren wrote on Jul 20^th, 2012, 6:41pm:

the chip is switch-cap circuit. and using the cadence spectreRF do pnoise analaysis. the noise summary shows that there are three switchs contribute above 70% of the total noise. the noise type are rs and rd. does thes make sense? what is the rs/rd noise? how to fix this?

the switch is paralleal of the PMOS and NMOS. both size is 2.2u/0.8u.

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