Hi, currently tools, IP, testbenches, models, etc. are often separated. I think for most designs a solution proposal exists. Would be great to start from this and refine step by step:

Image you want to design a block (op-amp, LNA, ADC, etc.):

Current tools are not really spec-driven, so a much better starting point would be a testbench, with stimuli, output definitions, simulator setup, etc. Of course that testbench needs to include a DUT, like a verilog-ams model. There you can check if DUT fits into system, refine, add further specs, etc.
Then you can replace the model by a real circuit from a scalable generic pdk library with builtin search function (like high-performance, low-power, low-voltage, ...).
Check TBs with real DUT again, vs corners, in Monte-Carlo, do sweeps, etc.  
Now parametrize the DUT & run optimizations. Try different toplogy proposals.  
Next prepare layout with constraints. Translate design to target pdk.
Do placement, wiring, DRC, lvs, extraction.
Check extracted performance, re-optimize.
Document the block for later re-use.

Currently a designer highly relies on his experiences and acts as a hunter - not bad for me, but in current A-MS design environments you have to care for almost all things for yourself: Put everything together, check what is not possible (WPE, STI, ESD, mismatch, parametrizations, fight with expressions not working in MC, simulation of reciprocal mixing noise, efficient pll simulation, fight with slow optimizers...), doing things again and again.

I think it would be not to difficult to put these things together, e.g. Cadence has many behavioral libs, but allmost all models are coming wo. testbenches.
Of course, also software itselfs needs improvements, e.g. even if you have all this, an existing ADEGXL setup is very hard to migrate, allways you have to go back into all ADEL sub-setups.

What do you think?

Bye Stephan