Designer’s Guide Community

RobG Community Fellow Offline Posts: 569 Bozeman, MT	Re: Gain-boosting cascode_zeros Reply #15 - Jul 21^st, 2011, 6:02am Bult and Gelen, "A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain," JSSC, Dec 1990. Here is a pdf: http://courses.engr.illinois.edu/ece483/bult.pdf It is a classic paper.
Back to top	IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: Gain-boosting cascode_zeros
Reply #16 - Jul 22^nd, 2011, 12:56am

RobG wrote on Jul 21^st, 2011, 6:02am:

Bult and Gelen, "A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain," JSSC, Dec 1990.

Here is a pdf: http://courses.engr.illinois.edu/ece483/bult.pdf

It is a classic paper.

Rob,

Since you have rekindled this thread with your post, I might as well add a comment on what we were discussing earlier regarding the bandwidth of the auxiliary amp.

If you see Section III on high-frequency behavior, then the authors are saying that the auxiliary amp does not need high bandwidth, and this is probably the point that is confusing. They are only speaking of stability at this point. One needs to scroll down to Section IV on settling behavior where the authors finally point out that the auxiliary amp needs to be faster than the main amp in order for the gain boosting to be of any use.

Regards

Vivek

Back to top

IP Logged

harpoon

Senior Member

Offline

Posts: 112
Hampshire

Re: Gain-boosting cascode_zeros
Reply #17 - Jul 26^th, 2011, 7:31am

fonseca.ha wrote on Jun 17^th, 2011, 12:51am:

About an intuitive way to get the number of poles and zeros. The number of poles is normally the same as the number of nodes. The number of zeros is normally equal to the number of direct branches between the input and output.
Regards,
Humberto

Here is how i work out poles and zeroes ... pls correct me if i am wrong.

Trace signal path from input to output.
no. poles = number of cap between signal path and ground
no. zeroes = number of cap in series with the signal path.

so there should be 3 poles and 3 zeroes (RHP) ... ignoring what it is connected to at the output and only considering Cgs and Cgd

comments ?

Back to top

IP Logged

CMOS_Jebas

New Member

Offline

Posts: 1
Bangalore

Re: Gain-boosting cascode_zeros
Reply #18 - Aug 27^th, 2012, 2:52am

Hi,

I want to discuss in the prespective of "designing gain boosted opamp for driving SC network".(pipelined ADC)

Thanks for Vivkr, for brief description.

I have two points to discuss;

1. From my simulation results and understanding;
. Pole-Zero doublet will occur when;
Main opamp UGB < Auxillary Opamp UGB
2. As mentioned by Vivkr,
If it is a transient respose(swing is more) then
Main opamp UGB < Auxillary Opamp UGB (should be)
Since Auxillary Opamp controlling node is isolated by cascoded transistor. Voltage swing At this node is less.We can say it as small signal swing. So, the above mentioned contion( Main opamp UGB < Auxillary Opamp U) is not at all necessary(I think). Auxillary opamp bandwidth is related to worst case signal swing occuring at cascoded node.

So as a conclusion;

Main opamp UGB > Auxillary Opamp UGB
. You can get rid off pole-zero doublet
. Without compromising transient response.(since it is small signal)

Back to top

IP Logged

tenso

Junior Member

Offline

Posts: 30
USA

Re: Gain-boosting cascode_zeros
Reply #19 - Feb 21^st, 2017, 10:44am

nrk1 wrote on Jun 20^th, 2011, 8:38pm:

* main amp BW < aux amp BW

Slight correction to the above(maybe this is what was meant):
Closed loop BW of the amp < aux amp unity gain frequency

The aux amp is in unity feedback. The main opamp may not be. So it is possible for main opamp unity gain frequency to be more than the aux amp unity gain frequency and still things to work out fine. The closed loop bandwidth of the circuit using the main opamp is (feedback fraction) * (main opamp unity gain frequency). In Fig. 3 of the paper, the unity gain frequency of the aux amp is less than the unity gain frequency of the main amp. But Fig. 5 shows that the former is more than the _closed loop bandwidth_ of the main amp. This is also clearly stated in the paragraph starting with "Our approach here ..." in Section IV.

* aux amp BW < main amp second pole

This inequality if not required for stability. For instance, things would be just fine if the aux amp was ideal(infinite bandwidth). There will be a pole followed by a zero due to the aux amp's unity gain frequency and because of this, the phase dips down and back up. If the maximum dip coincides with the unity loop gain frequency[ = (feedback fraction) * (main opamp unity gain frequency) ], stability will be affected, but it won't matter if it occurs at a much higher frequency.

I believe Sackinger and Guggenbuhl published this before Bult.

Cheers

sorry to dig up an old thread, but I was reading up on gain boosted opamps and the settling response issues which can arise from the pole zero doublets.

Just a clarification here, when people are referring to the main amp. in this thread, are you guys talking about the amplifier itself without gain boosting or the amplifier with the gain boosted included? If I understand it right, it is the former.

Back to top

IP Logged