Hi All,

We have a signal processing chip (4 channel ADC + PLL + serializer) in 0.18um technology. The chip consumes about 170mA current. The VCO of the PLL works at 1.3GHz (differential ring oscillator, followed by duty-cycle correction circuit), the data output rate is 2.6Gbps.

The PLL and digital circuit share the same regulator and the regulator can be bypassed. During characterization, we found that the PLL have two much jitter and we have problem to send data out. We check
the power supply of the PLL, it seems that the power supply is very bad. There is a lot of bounce (300mV) in both power supply and ground. Even if we bypass the regulator, the bounce is the same as with regulator (please refer to the power supply waveform in the attachment). I am wondering why there is such big bounce? One reason I think is that it is due to the ESL of the decoupling cap connected between the power and ground because deltaV=L*dI/dt. If dI/dt is big, then very small L would create big bounce. If this is the
reason, we can maybe using small decoupling cap (means small ESL). Is there any other reason for the bounce? Any idea are welcome.

We are going to change the mask to address the jitter issue of the PLL. One way is to put deep NWELL underneath the PLL to isolate its substrate from the chip substrate. But what about the power supply and ground of the PLL? Should we put a regulator only for PLL to use? Inside the chip, the ground of the PLL is separated from other circuits, but all grounds were connected together in the PCB board. I am wondering what people usually do with the power and ground for high speed PLL? Any idea are welcome.

Thanks,

Lunren

hi,
as maynak said hanging both digital and analog to an regulator is not good idea,
1.whats your regulator psrr and whats the ripple on the regulator. BY finding the ripple and vco frequency senesetivity you estimate whats the impact of the vco on jitter
2.Try to increase the decap at the regulator O/P.
3.Do you have any probing points for pll critical nodes like vcontrol, if so check the ripple and through Kvco also you can estimate impact.
4.Whats the Kvco?
5. Is there any correlation for supply noise frequency and digital stuff frequency, if so you can suspect ESl I guess ESL.

Thanks.

hi,
as maynak said hanging both digital and analog to an regulator is not good idea,
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The PSR of the regulator is only -5dB at the frequency that VCO works (1.3GHz). Maybe we need change the regulator structure so that we can have very good PSR at very high frequency?
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Because the dropout is only 200mV, so the size of the PMOS is big which make the dominant pole locates at the gate of the PMOS. So if we increase the decap too much, it would be unstable.
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Yes, we use off-chip loop filter. We can probe vctrl.
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3GHz/V
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From the attachment, we can see that there are two frequency on the power profile, 12MHz and 100MHz. But in the digital circuit, we don't have such a working frequency.

raja.cedt & Mayank,

Do you usually power the PLL (especially high speed PLL) with a separate regulator?

Thanks.

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Yes we do.

Separate LDOs for CPUMP & VCO & other internal blocks of pll are required in only v tight jitter spec plls.
Usually a single separate ldo for pll's analog supply is enough.

--M

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Hi Mayank, should the separate LDOs for CPUMP & VCO have very good power supply rejection at ALL frequency? How do you define the PSR spec for PLL? Any comments on the PSR profile (pink on in the attached file) of the regulator we will be using for the PLL are welcome.

Thanks,

Lunren

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Chielfy by vco supply current profile, & reference spur suppression.

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Average. Could be improved if needed.