The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 19th, 2024, 12:23am
Pages: 1
Send Topic Print
nanosim memory design (Read 3352 times)
seahs
Junior Member
**
Offline



Posts: 16

nanosim memory design
Nov 15th, 2010, 7:47pm
 
how to calculate the sram bitline wiring capacitance ?

It seems the total bitline cap is very small in my design, about 100fF for a bitline with 1024 memory cells connected in 130nm. I am wondering if the metal layer cap is included.

Thanks for any suggestion.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.