Hi all,

I have a question regarding static power calculation for a or2 gate.
Let say that A,B = 0 and only subthreshold leakage is observed.

regarding the attach schematic, can i write :

I_t1 = PMOS sat= µ.Cox.(W₁/2L) (Vsg + Vt)²
I_t2 = PMOS sat= µ.Cox.(W₂/2L) (Vsg + Vt)²
I_t3 = NMOS sub= µ.Cox.(W₃/L) Vt² e((Vgs-Vth)/nVt)
I_t4 = NMOS sub= µ.Cox.(W₄/L) Vt² e((Vgs-Vth)/nVt)
I_t5 = PMOS sub=µ.Cox.(W₅/L) Vt² e((Vgs-Vth)/nVt)
I_t6 = NMOS sat= µ.Cox.(W₆/2L) (Vgs - Vt)²

Please let me know if you think that these equation are correct,
and also i m not sure about the way to add them.

do i have to add them all to find the static power ?

thank you for your time,

David.



ps : Let me know if you have an example of this kind of calculation