The Designer's Guide Community Forum - PLL transfer function plot

casual Senior Member Offline Posts: 122	PLL transfer function plot Jul 27^th, 2010, 12:19am Can cadence spectreRF plot out the PLL transfer function?
Back to top	IP Logged

sheldon Community Fellow Offline Posts: 485	Re: PLL transfer function plot Reply #1 - Jul 27^th, 2010, 4:57am Casual, Can you be more specific about what you would like to do? Do you mean plot a transfer function? Do you mean simulate a PLL and generate a transfer function? Which transfer function are you looking to plot? BTW, I believe that vendor specific questions go in the simulators section. Best Regards, Sheldon
Back to top	IP Logged

casual

Senior Member

Offline

Posts: 122

Re: PLL transfer function plot
Reply #2 - Jul 27^th, 2010, 5:50am

I would like to obtain input/output transfer function of a PLL, eg: H(jw) vs freq and check bandwidth & overshoot response. I can make it in matlab but I do not know how to generate it in spectre. I believe it can be simulated.

PS: thx for reminding me that this post should be in simulator session. I do not know how to move it to there.

Back to top

IP Logged

vp1953

Community Member

Offline

Posts: 55

Re: PLL transfer function plot
Reply #3 - Jul 27^th, 2010, 10:21am

Hi Casual,

I was told by one of the Cadence technologists that anything that can be done in Matlab can also be done in Spectre, perhaps not so conveniently. Here might be one way - model the PD (and the VCO as well as the divider) using verilog-ams, the loop filter could be used as a circuit block. The use stability analysis (analysis>stb) for gain and phase plots - this option requires placing a probe somewhere in the feedback loop.

If you do find an easier way, do let us know.

Back to top

IP Logged

casual Senior Member Offline Posts: 122	Re: PLL transfer function plot Reply #4 - Jul 28^th, 2010, 12:02am i know verilogA can model the laplace function. The results will be the same as in matlab. But it depends on how accurate we model it. Therefore it is great if we could simulate directly the PLL to get the transfer function.
Back to top	IP Logged

sheldon Community Fellow Offline Posts: 485	Re: PLL transfer function plot Reply #5 - Jul 28^th, 2010, 10:30pm Casual, Look in samples/pllLib for examples of how to implement phase domain models for a PLL. Best Regards, Sheldon
Back to top	IP Logged

casual Senior Member Offline Posts: 122	Re: PLL transfer function plot Reply #6 - Jul 30^th, 2010, 11:00pm thx, i will take a look
Back to top	IP Logged

pancho_hideboo

Senior Fellow

Offline

Posts: 1362
Real Homeless

Re: PLL transfer function plot
Reply #7 - Aug 7^th, 2010, 3:50am

If you can build "State Averaged Model" for target DUT, you can adopt conventional AC Analysis in any SPICE type Simulator.

See http://edocs.soco.agilent.com/display/ads2009/Open+and+Closed+Loop+Simulation+of...
Here all blocks are treated as linear state averaged model.
"LinearVCO" is a linear model of a VCO.
"LinearPFD" is a linear model of a phase/frequency detector.
"LinearPFD2" is a 2-input linear model of a phase/frequency detector.
"LinearDivider" is a linear model of a divider.

This "State Averaged Modeling" is well known as "Describing Function Method" or "Equivalent Transfer Function Method"
in Nonlinear Control Theory.

Equivalent Lowpass Model of RF Bandpass System is this "State Averaged Modeling".
Phase Domain Model of PLL is also this "State Averaged Modeling".
http://www.designers-guide.org/Forum/YaBB.pl?num=1237145096/8#8

Back to top

Kita━━━━━━(ﾟ∀ﾟ)━━━━━━ !!!!!
http://www7.plala.or.jp/ungeromeppa/flash/kita.html
http://www.youtube.com/watch?v=mjIxGh55bMM&feature=related

IP Logged

Ken Kundert

Global Moderator

Offline

The Spectre

Posts: 1444
San Jose

Re: PLL transfer function plot
Reply #8 - Aug 7^th, 2010, 12:57pm

It is still not clear what you want to do. It is possible to build a phase-domain model of your PLL and simulate in any simulator that has a reasonable modeling language, including any circuit simulator that implements Verilog-A. You could also use tools like Matlab. Or you can code the model up your self in any programming language, such as Python or C. However, this is a simplified model; very simplified as you will come to understand when you go to build the models of the various components. This process is described in some depth in http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf.

Alternatively, you might be looking to do a transistor-level simulation and extract the transfer function. That is possible with RF simulators such as SpectreRF. Basically, you set up the PSS analysis so that its initial transient interval (set by tstab) is long enough to take the PLL into lock, then it computes the periodic steady-state solution. For this to be possible your PLL must satisfy a few criteria. First, it must have a periodic steady-state solution; so your PLL must have no deadzone or fractional-N architectures. And it must be practical to compute the steady-state solution, and so if there is a divider in the loop, its divide ratio must be relatively small. Once you have the steady-state solution, you can run any of the small-signal analyses that work with PSS. Those include PAC, PXF, PSTB, and of course, PNoise. They perform the AC, transfer function, stability, and noise analyses respectively.

-Ken

Back to top

IP Logged