The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines. Nov 19th, 2017, 4:30am
  HomeHelpSearchLoginRegisterPM to admin  
 
Pages: 1
Send Topic Print
Post layout simulations (Read 4134 times)
raja.cedt
Senior Fellow
******
Offline



Posts: 1516
Germany
Post layout simulations
Jul 03rd, 2010, 3:55am
 
hi,

i have designed an LC vco based PLL in TSMC45gs. Silicon Results are  matching with RC Simulations(5g is the simulated result and 5.09 is the silicon result) but RCC based simulations are showing that 5.3g. Can any one please explain out of RC,RCC which one is best.

Thanks,
Rajasekhar.

Back to top
 
 
View Profile WWW raja.sekhar86   IP Logged
ACWWong
Community Fellow
*****
Offline



Posts: 539
Oxford, UK
Re: Post layout simulations
Reply #1 - Jul 3rd, 2010, 11:11am
 
I'm guessing raja means 5GHz and that RCC means Resistor Capacitor Coupled extraction.

Raja,

Given this assumption, I think you have answered your own question since your silicon matches your RC extracted result better than the RCC result. But remember many other things impact the frequency you are measuring (i.e. parasitic mutual/series inductances, process skew, mismatch etc. measurement technique, loading, packaging etc.etc.).

As to which extraction is better is very circuit, layout, frequency, rule, tools etc. dependant so its not really possible to know to make a sweeping generalisation of which is better for say VCO's....
It is the designer's decision based on the circuit and layout and which tools and rules are at his/her disposal as to which extraction to run and which extraction is most appropriate.
And when silicon is measured and that the process skew is fed back into the simulation, you can find out which extraction worked best ... in your case it seems RC !

cheers
aw
Back to top
 
 
View Profile   IP Logged
raja.cedt
Senior Fellow
******
Offline



Posts: 1516
Germany
Re: Post layout simulations
Reply #2 - Jul 3rd, 2010, 7:45pm
 
hi ACWWong
thanks for your reply. Haveyou seen any silicon data matches with RC? i didn'tunderstand the following fromyour reply.
It is the designer's decision based on the circuit and layout and which tools and rules are at his/her disposal as to which extraction to run and which extraction is most appropriate.

For post layout simulations i will prefere RCC if time is there otherwise i will go with CC.

Thanks,
Rajasekhar.
Back to top
 
 
View Profile WWW raja.sekhar86   IP Logged
aaron_do
Senior Fellow
******
Offline



Posts: 1398

Re: Post layout simulations
Reply #3 - Jul 5th, 2010, 6:28am
 
Hi,


could somebody explain the difference between RC and RCC parasitic extraction? I searched around for a few documents but couldn't find anything...


thanks,
Aaron
Back to top
 
 

there is no energy in matter other than that received from the environment - Nikola Tesla
View Profile   IP Logged
raja.cedt
Senior Fellow
******
Offline



Posts: 1516
Germany
Re: Post layout simulations
Reply #4 - Jul 5th, 2010, 7:32am
 
hi Aaron,

RCC means you will get node to ground cap,node to node cap and node to node resistance.
RC means node to ground cap and node to node resistance, here actually extraction tool will be doing is it splits coupling cap and added to node to ground cap.

Thanks,
Rajasekhar.
Back to top
 
 
View Profile WWW raja.sekhar86   IP Logged
aaron_do
Senior Fellow
******
Offline



Posts: 1398

Re: Post layout simulations
Reply #5 - Jul 5th, 2010, 8:27am
 
thanks!
Back to top
 
 

there is no energy in matter other than that received from the environment - Nikola Tesla
View Profile   IP Logged
Lex
Senior Member
****
Offline



Posts: 201
Eindhoven, Holland
Re: Post layout simulations
Reply #6 - Jul 6th, 2010, 1:54am
 
I've always been skeptical about resistance calculations of extractors. Usually it checks the wires with an internal database of patterns, so it's not actually field solving. If not too cumbersome, you can check some critical paths by hand to see whether it did a good calculation.
Back to top
 
 
View Profile   IP Logged
love_analog
Senior Member
****
Offline



Posts: 101

Re: Post layout simulations
Reply #7 - Jul 29th, 2010, 6:51am
 
Raja
RCC is always more accurate since it resembles the circuit more. Remember there could be other effects (which are not modeled) which cause the RC to match silicon better. This doesn't make RC better in all cases.

For instance, suppose the varactors are not modeled correctly (in fact I know that is usually the case) and they could make RC match silicon better than RCC
Back to top
 
 

loveanalog.blogspot.com
The Power of Analog
View Profile   IP Logged
monglebest
New Member
*
Offline



Posts: 4
Austin
Re: Post layout simulations
Reply #8 - Oct 5th, 2017, 1:45pm
 
May I know why not just ran the most detailed extraction simulation, like RCC? I also see people report results for C+CC, what does that mean as well?

Why there are so many different extraction setting?
Back to top
 
 
View Profile   IP Logged
Horror Vacui
Community Member
***
Offline



Posts: 52

Re: Post layout simulations
Reply #9 - Oct 22nd, 2017, 11:54am
 
Speed. Both extraction and simulation. R extraction creates countless nodes, which slows down the simulation, and also gives little feedback to the designer which caps are big. For low frequency circuits C+CC is usually enough. A simple C might give you a faster feedback about the critical wirings and the expected capacitances. Maybe I am a rare and endangered animal, but I always look in the generated netlist. There are meaningfully less capacitors, so it is easier to digest. Though I use almost C+CC.
If you use very high frequency (mmWave) than you might consider a field solver.
Though the best tool is a capable engineer who knows the critical nodes and reduces the capacitances as much as possible. Even if the tool tells you that it is not enough you can not improve the layout any more... Also if your circuit performance depends heavily on the extraction value, then it might not be a robust solution, which implies some programming capability or a post-measurement adjustment.
Back to top
 
 
View Profile   IP Logged
A Kumar R
Community Member
***
Offline



Posts: 59
India
Re: Post layout simulations
Reply #10 - Nov 2nd, 2017, 5:31am
 
Hi Raja,

It is somewhat interesting to me that when RCC-extracted netlist is simulated then the PLL locks for a higher freq?

i think RCC contains more caps compared to RC..isn't it?

Back to top
 
 
View Profile   IP Logged
Maks
Community Member
***
Offline



Posts: 36
San Jose
Re: Post layout simulations
Reply #11 - Nov 5th, 2017, 10:08am
 
Lex wrote on Jul 6th, 2010, 1:54am:
I've always been skeptical about resistance calculations of extractors. Usually it checks the wires with an internal database of patterns, so it's not actually field solving. If not too cumbersome, you can check some critical paths by hand to see whether it did a good calculation.


Internal database for patterns is used only for capacitance calculations, not for resistance (as far as I know).

Various extraction tools handle resistance extraction differently, but most of them use one-dimensional extraction algorithm, in various approximations, where a metal line is considered to be one-dimensional, and is fractured along the length.  Then resistors of known length and (estimated) width are created and added to the R network (then, parasitic coupling capacitances are added to fracturing points).

This approach is quite accurate and works really well when metal shapes are really one-dimensional - i.e. narrow and long, and when current flow in metal lines is really one-dimensional. This is the case for standard cells, digital designs, etc.

In case of analog circuits, and especially - power ICs (PMICs), metals are often wide, connected to each other through large 2D arrays of vias, and current flow may not be one-dimensional. In this case, 1D R extraction will have large inaccuracies.

(Note that not all 1D R extraction tools are equal - they are using quite different algorithms, and some are more accurate than others.)

That's why analog designers are often suspicious about the accuracy of R extraction. But, if you know the limitations of the extraction tools, and if you have some other tools at hand, situation may not be that bad.

Some extraction tools (like Quantus QRC) have an option to do 2D R extraction on wide metal layers.

There are also several other layout analysis tools that perform more accurate and more physical discretization (meshing) of complex metal / via shapes, to get very accurate Resistance and current density simulations. Please refer to this thread on EDABoard web site:

http://www.edaboard.com/showthread.php?t=304145&highlight=r3d

Max
Back to top
 
 
View Profile   IP Logged
Maks
Community Member
***
Offline



Posts: 36
San Jose
Re: Post layout simulations
Reply #12 - Nov 5th, 2017, 10:15am
 
Horror Vacui wrote on Oct 22nd, 2017, 11:54am:
Speed. Both extraction and simulation. R extraction creates countless nodes, which slows down the simulation, and also gives little feedback to the designer which caps are big. For low frequency circuits C+CC is usually enough. A simple C might give you a faster feedback about the critical wirings and the expected capacitances. Maybe I am a rare and endangered animal, but I always look in the generated netlist. There are meaningfully less capacitors, so it is easier to digest. Though I use almost C+CC.
If you use very high frequency (mmWave) than you might consider a field solver.
Though the best tool is a capable engineer who knows the critical nodes and reduces the capacitances as much as possible. Even if the tool tells you that it is not enough you can not improve the layout any more... Also if your circuit performance depends heavily on the extraction value, then it might not be a robust solution, which implies some programming capability or a post-measurement adjustment.


Due to the complexity of modern designs, "capable engineer" combined with the right tools, and knowing the issues of these tools and how to get around that, may be the best solution.

IN latest technologies (16nm and below), design performance is degraded by parasitics by up to 2x-3x (speed, frequency, etc.), so parasitics cannot be ignored, and should be accounted for as early as possible, in the design flow.

People looking inside extracted netlists are indeed rare and endangered animals, the existing tools and flows were not designed having these people in mind Smiley

There are some tools though that help these people to quickly review, analyze, debug and fix layout parasitics issues.
Back to top
 
 
View Profile   IP Logged
Maks
Community Member
***
Offline



Posts: 36
San Jose
Re: Post layout simulations
Reply #13 - Nov 5th, 2017, 10:38am
 
A Kumar R wrote on Nov 2nd, 2017, 5:31am:
Hi Raja,

It is somewhat interesting to me that when RCC-extracted netlist is simulated then the PLL locks for a higher freq?

i think RCC contains more caps compared to RC..isn't it?



more capacitance does not necessarily mean lower frequency.

As a simple example - if a significant fraction of the total capacitance of a net A goes to net B, and net B is always at the same potential as net A, these coupling capacitances have no electrical effect, and delays along net A are shorter than if you consider all coupling capacitances of A going to ground.

In general, RCC (C coupled to other nets) extraction is (much) more accurate than RC (all C grounded), but there are many reasons why there is a discrepancy between simulated and measured results, and why RC results "accidentally" (or misleadingly) may be closer to the measured ones.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Trouble viewing this site? Copyright © 2002-2014 Designer's Guide Consulting. 'Designer's Guide' is a registered trademark of Designer's Guide LLC. All rights reserved.

Our colleges are not as safe as they seem. Sexual assault is pervasive and the treatment of the victim by the adminstration is often as damaging as the assault: Campus Survivors, Campus Survivors Forum.

Some of our other sites that you might find useful: QuantiPhy.