For improving yields againt process variations, I use laser fuse trimmings for some register's settings.
I would like to emulate this operation and confirm yields after trimmings using Monte Carlo Analysis.

Assume trimmings are done according to Vth value of MOS FET.
This is actually done by DC analysis under Monte Carlo Trials.

After trimmings, I would like to evaluate dynamic characteristics such as Gain or Output Power Level by using AC analysis or HB analysis under Monte Carlo Trials.

How can I do these analysis using Monte Carlo trials ?

For Corner Analysis, I can easily do AC analysis or HB analysis with trimming register's values as design variables.
But I would like to confirm yield's improvemnet by trimmings under more random process variations.
Here trimmings are also random.


I can accept any simulator engine and any post processing environment.

sheldon wrote on Jun 13^th, 2010, 5:14am:
Do you understand my need correctly ?
My need is like following:

for(MC_Trial=1; MC_Trial<=1000; ++MC_Trial) {
    // MC_Trial=n
    DC Analysis in random variables set for "MC_Trial=n"
    Tran Analysis in same random variables set as DC Analysis
    and design prameter value's set determined by DC Analysis.
}

I'm now trying my need by using Golden Standard HSPICE.
We can not use full ability of HSPICE if we use it in Cadence ADE.

Cadence Spectre's netlist for MonteCarlo Analysis is like following.
Quote:

I don't think there is a special ability in Cadence Spectre for my need.

If task of my need is possible to resolve without adding special ability to simulator engine,
it can be possible by any simulator with Ocean Scripts or Unix Shell Scripts.

I will survey Cadence IC6.1.4.

I can make simulation methodology for resolving my need now.

I do mutiple monte carlo trials without using mutiple trials run provided for Monte Carlo ability.
Instead, I do multiple monte carlo trials by Ocean Scripts or Unix Shell Scripts using single monte carlo trial with fixed seed and incrementation of "Starting Run #" for random variables.

Here I use some Verilog-A modules for dumping design parameter's values as results of process variation judgement in DC analysis.
This task of setting design variables according to DC Analysis results is also possible without using Verilog-A module.

I have to merge many single trial monte carlo files to one file.
If monte carlo trial number is 1000, 1000 files are created.
But I don't do that, instead I add result to one file after each trial, so it does not create many files.
It is easy to do this if we use ascii text data.

I can apply this methodology for any simulator such as Synopsys HSPICE, Agilent RFDE(ADSsim), Agilent GoldenGate and Cadence Spectre, etc.

Agilent GoldenGate provide an utility command, "mc_merge" for Running Monte Carlo Trials in Parallel.
If I use this, I can merge results as binary data very easily.

sheldon wrote on Jun 14^th, 2010, 6:14am:
No, I don't need it at all.
If I use Synopsys HSPICE, I can do more superior tasks than "cdsSpice" or "Specte + SpectreMDL" can do.

I can create more versatile scripts which are not restricted to specific vendor's simulator by myself.

sheldon wrote on Jun 15^th, 2010, 2:15am:
What did I miss ?
I can't miss any point since there can not be any interest or novel point.

sheldon wrote on Jun 14^th, 2010, 6:14am:
I don't need any support which is no more than tool usage and I can easily understand if I read documents.
I don't think our local Cadence support can provide something more than easy tool usage which I can easily find out only if I read documents.

Again If I use Synopsys HSPICE, I can do more superior tasks than "cdsSpice" or "Spectre + SpectreMDL" can do.
List up tasks which can not be possible by HSPICE but possible by "Spectre + SpectreMDL", if any.

Again I can create more versatile scripts which are not restricted to specific vendor's simulator by myself without such valueless support.


Previously you sent me a mail that "VPCD was remarkably improved, so contact local support",
after http://www.designers-guide.org/Forum/YaBB.pl?num=1169632704/8#8.

But I could not find out any remarkable improvement in VPCD(Virtuoso Passive Component Designer) at all.
http://www.edaboard.com/viewtopic.php?t=335639

At last, VPCD has been EOL.
http://www.designers-guide.org/Forum/YaBB.pl?num=1244552575

pancho_hideboo wrote on Jun 13^th, 2010, 7:37am:


The reason why it is not in the documentation is because this is an engineering release in IC614, and we wanted to work with customers to get their valuable feedback before releasing it to everyone. That's why Sheldon recommended contacting your local Cadence office.

It's controlled via a cdsenv variable, and the capability is fully released in the upcoming IC615 release (and is then documented).

It allows you to do exactly this:

Quote:


In fact you can have complex calibration steps at each point in the monte-carlo, for example doing a binary chop calibration run involving multiple simulations. I've presented this at a Technology on Tour, and it was also presented at a recent CDN Live! event in 2010, I believe.

Regards,

Andrew.