The Designer's Guide Community Forum - question about vco modulation simulation

xuhaoz

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question about vco modulation simulation
May 18^th, 2010, 6:15am

Hi, guys,

I have question about vco modulation simulation.

I have a test bench including vco , divider and buffer. The vco is running at 3.3GHz, and vco output is connected to /2 divider and finally feeds to buffer. At buffer output the frequency is about 1.86GHz. At the Vco supply, there is a 52MHz interference, i am curious about how this interference is modulated by VCO and how can i observed at 1.86GHz +/- 52MHz ? What simulation should I run to see the actually sidebands of 1.86GHz ? Note: there is only one signal source 52MHz at supply in my testbench.

Thank you very much.
james

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pancho_hideboo

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Re: question about vco modulation simulation
Reply #1 - May 29^th, 2010, 12:22am

xuhaoz wrote on May 18^th, 2010, 6:15am:

At the Vco supply, there is a 52MHz interference,
i am curious about how this interference is modulated by VCO
and how can i observed at 1.86GHz +/- 52MHz ?
What simulation should I run to see the actually sidebands of 1.86GHz ?
Note: there is only one signal source 52MHz at supply in my testbench.

There are two options for treatment of 52MHz signal.

(1) Treatment of 52MHz signal as Small Signal in Small Signal Analysis subjected to master Large Signal Autonomous Steady State Analysis.

(2) Treatment of 52MHz signal as Large Signal in two Large Signals Autonomous Steady State Analysis.

See the followings.
http://www.designers-guide.org/Forum/YaBB.pl?num=1204880225/5#5
http://www.designers-guide.org/Forum/YaBB.pl?num=1151438219

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xuhaoz New Member Offline Posts: 5	Re: question about vco modulation simulation Reply #2 - May 29^th, 2010, 6:28am Hi, Pancho Thank you very much. I have made the simulation work. BTW, another question, if I have only vco oscillating at 3GHz and i have a few N dividers running to get lower freq clock. I want observe some internal node freqeuncy spectrum . What simulation should I use ?
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pancho_hideboo

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Re: question about vco modulation simulation
Reply #3 - May 29^th, 2010, 6:37am

xuhaoz wrote on May 29^th, 2010, 6:28am:

What simulation should I use ?

Autonomous Large Signal Steady State Analysis.

If you use Agilent ADSsim(RFDE), use HB Analysis.

If you use Agilent GoldenGate, use CR Analysis.

If you use Mentor EldoRF, use ".SST" Analysis.

If you use Synopsis HSPICE RF, use ".HB" Analysis.

If you use Cadence Spectre, use PSS Analysis.

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xuhaoz New Member Offline Posts: 5	Re: question about vco modulation simulation Reply #4 - May 29^th, 2010, 8:13am Hi, if I use pss in cadence, can i observe freq for example fvco +/- 0.5*fvco , fvco +/- 52MHz, etc. There are lots of frequency content in my circuit, such as fvco/2, fvco/4, fvco/60, etc. Can I use pss to observe all these frequencies?
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pancho_hideboo

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Re: question about vco modulation simulation
Reply #5 - May 29^th, 2010, 8:23am

xuhaoz wrote on May 29^th, 2010, 8:13am:

Hi, if I use pss in cadence

What do you mean by "pss in cadence" ?
We can use many simulators such as HSPICE, BDA's Analog FastSPICE RF, ADSsim and GoldenGate in Cadence ADE.
Do you mean "PSS in Cadence Spectre" ?

If there is a common divisor frequency in {fvco +/- 0.5*fvco, fvco +/- 52MHz, fvco/2, fvco/4, fvco/60}, you might be able to use PSS which is Large Signal Steady State Analysis based on one fundamental frequency.
If "fvco +/- 52MHz" are not included in frequencies or you treat 52MHz signal as small signal, a common divisor frequency is fvco/60.

Again there are two options for treatment of 52MHz signal.
How do you treat 52MHz signal, small or large ?
Do you understand meaning of "small signal" and "large signal" in simulation ?

Again surely see http://www.designers-guide.org/Forum/YaBB.pl?num=1204880225/5#5

The followings are general notes for you.

- Always describe correct tool's name and vendor's name which you use as tool or simulator.
- Don't do multiple posts which are same content.
- Don't request source code or behavioral model without any efforts.
- There are many simulators which have analyses called as PSS, PAC and Pnoise.
- Describe in detail with using correct terminologies.
- Warnigns are different from Errors.
- ADS is not name of simulator.
- There is no tool which name is Cadence.
- Don't use Direct Plot of Cadence ADE blindly without knowing definition.
- All gains in Direct Plot of Cadence ADE are "right", "true" and "practical" voltage gain.
- Don't mix up Simulation with Post Processing. They are completely different phase.
- MATLAB are different from Simulink.
- Learn measurements using actual instruments. Not "EDA Tool Play

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xuhaoz

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Re: question about vco modulation simulation
Reply #6 - May 29^th, 2010, 10:17am

Ok, I will remember.

I mean using pss simulation in virtuoso 6.1. I have no any ideal signal source in the circuit. Only a vco running at a few GHz, but I have many dividers. I think if the circuit doesn't have a good isolation between each block or the circuit is calibrating the divide ratio while vco is running, it might generate lots of unwanted frequency. I want to simulate this . I suspect the circuit will generate fvco +/- fdiv with lots of dividers together, because at divdiers output, i have 26MHz, 52MHz, 114MHz, etc, so I want to prove it in the simulation .

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pancho_hideboo

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Re: question about vco modulation simulation
Reply #7 - May 29^th, 2010, 10:22am

xuhaoz wrote on May 29^th, 2010, 10:17am:

I mean using pss simulation in virtuoso 6.1.

"virtuoso 6.1" is not name of simulator.
We can use many simulators such as HSPICE, BDA's Analog FastSPICE RF, ADSsim and GoldenGate in virtuoso 6.1.
Again use correct terminologies.

xuhaoz wrote on May 29^th, 2010, 10:17am:

I have no any ideal signal source in the circuit.
Only a vco running at a few GHz, but I have many dividers.
I think if the circuit doesn't have a good isolation between each block

Even if the circuit doesn't have a good isolation between each block, fundamental frequency of circuit is fvco/N. Here N is total divide ratio.

See http://www.designers-guide.org/Forum/YaBB.pl?num=1268969030/7#7

xuhaoz wrote on May 29^th, 2010, 10:17am:

or the circuit is calibrating the divide ratio while vco is running, it might generate lots of unwanted frequency.

If divide ratio truely changes dynamically at random, use envelope analysis or transient analysis.
This case is not periodical state, although I don't think such analysis is required for your case.

xuhaoz wrote on May 29^th, 2010, 10:17am:

because at divdiers output, i have 26MHz, 52MHz, 114MHz, etc.

It seems fundamental frequency is 26MHz, although I don't know other frequencies which are "etc.".

I assume fvco is around 3120MHz, fundamental frequency is 3120MHz/120=26MHz.

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xuhaoz

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Re: question about vco modulation simulation
Reply #8 - May 29^th, 2010, 10:55am

Even if the circuit doesn't have a good isolation between each block, fundamental frequency of circuit is fvco/N. Here N is total divide ratio.

fvco/N ? so if I have N = 2,4, 8, ... 60, 62 etc. which is the fundamental freq ? 62 ? the highest number? for example, I should set guess osc freq to Vco/N in pss form , N is the largest number in my circuit, is that what you mean ?

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pancho_hideboo

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Re: question about vco modulation simulation
Reply #9 - May 29^th, 2010, 10:57am

xuhaoz wrote on May 29^th, 2010, 10:55am:

fvco/N ? so if I have N = 2,4, 8, ... 60, 62 etc. which is the fundamental freq ? 62 ? the highest number?
for example, I should set guess osc freq to Vco/N in pss form , N is the largest number in my circuit, is that what you mean ?

Yes, although still I don't know what simulator's PSS you use.

Again see http://www.designers-guide.org/Forum/YaBB.pl?num=1268969030/7#7

If you observe spurious frequecies which are not expressed as M*fund_freq in actual measurement, you should suspect parasitic oscillation in circuit, e.g. bias circuit.

See http://www.designers-guide.org/Forum/YaBB.pl?num=1268385779/3#3

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