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PLL Phase Noise Simulation (Read 6430 times)
Count
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PLL Phase Noise Simulation
Apr 13th, 2010, 7:06am
 
Hi, I know there are many different ways of simulating the phase noise of PLL, mostly involve the use of behavioural models. The way I am getting the phase noise performance is as follows:

1. Derive the noise transfer function of each sub-blocks by assuming the PLL to be a linear system.
2. Simulating the phase noise performance of each sub-blocks using pss/pnoise analysis.
3. Use matlab post-processing to sum up the noise contribution of each sub-blocks.

However, there are some concepts that I am not clear and do hope that I can find some guidance here.

Firstly, do I make use of the output noise(dB/Hz) or phase noise (dBc/Hz) when finding the noise contribution of each block? I find it confusing because the carrier frequency of each sub-block can be different. E.g. the VCO may be operating at 200MHz while the operating frequency of the PFD can be 10MHz. Furthermore, when deriving the noise transfer function of each sub-block, I do not see any carrier frequency comes into play.

Secondly, I am experincing some problems in getting the noise performance of PFD + CP. In my simulation setup, I am putting in two exact clock signals into the PFD and connecting a dc voltage at the CP output. The dc voltage is fixed at the nominal control voltage to the VCO when the PLL loop is locked. In this case, I am only able to get the output noise in current domain rather than in voltage domain. How do I get the output noise in voltage domain? If I connect the actual loop filter the the CP output, I am not able to fix the voltage at that node. I am also confused with the output carrier of the PFD + CP sub-block. Does it even exist? Because when PLL is locked, the PFD only outputs tiny UP and DOWN pulses that are then converted to a voltage level by the CP. How do I then get the phase noise of PFD + CP in terms of dBc/Hz?

I understand this is quite a lengthy post but I really do appreciate the help. Thanks!
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Ken Kundert
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Re: PLL Phase Noise Simulation
Reply #1 - Apr 13th, 2010, 10:53am
 
Concerning your first question, you need the noise in terms that are compatible with your transfer functions. Are your transfer functions written in terms of voltage or phase? Most of them are probably written in terms of phase. Another critical question you should be asking is should you be using the jitter feature (assumes a threshold).

For the PFD, your test setup is correct, and the output noise should be measured in terms of the current. You have two alternatives on how you use this noise. Either you can formulate a transfer function from the input of the loop filter to the output (which would map current to phase) and use the output noise directly, or you could refer the output noise back to the input and use the transfer function from the input to the output. In this case, the input-referred PFD/CP noise is a phase noise.

-Ken
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Count
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Re: PLL Phase Noise Simulation
Reply #2 - Apr 14th, 2010, 4:55am
 
Hi Ken, thanks for the prompt reply.

Replying to your first comment, I am deriving the transfer functions in terms of phase. I thought I read it somewhere that voltage and phase are interchangeable as far as phase noise is concerned. Anyway, let me describe to you how I obtain the transfer functions.

Assuming the PFD has a gain of Kf (units of Amps), the loop filter has a impedance of ZLF and the VCO has a transfer function of Kvco/s (units of Hz/V). Accordingly, the forward transfer function, G, is [(Kf x ZLF x Kvco)/s]. Subsequently, the noise transfer function of VCO output noise would then be 1/(1+G).

Based on the above model, should I be making use of output noise in terms of dB/Hz or dBc/Hz? May I also know what is the reason behind it? And also, I do not quite understand what do you mean by using the jitter feature. Pray elaborate more on this.

As for the PFD noise, the noise transfer function from the input of loop filter would be (1/Kf) x G/(1+G). Based on your explanation, I can make use of the PFD output noise in terms of current since the 1/Kf term in the transfer function cancels out the current units in the PFD output noise. Am I correct? Smiley

Thanks for the help!
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ussmueller
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Re: PLL Phase Noise Simulation
Reply #3 - Apr 15th, 2010, 6:56am
 
Hi,

I have a question concerning the simulation of your complete PLL. You mentioned that you are using PSS/ PNOISE analysis. To my understanding the phase domain models are small signal models, thus a noise simulation should be sufficient. Is this true? Am I missing something.

Thanks,
Thomas
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rfmems
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Re: PLL Phase Noise Simulation
Reply #4 - Apr 16th, 2010, 5:19am
 
ussmueller wrote on Apr 15th, 2010, 6:56am:
I have a question concerning the simulation of your complete PLL. You mentioned that you are using PSS/ PNOISE analysis.
Thomas


I suppose he was talking about how to get the noise from each building block, thus for some of them, PSS+PNOISE is necessary.
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rfmems
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Re: PLL Phase Noise Simulation
Reply #5 - Apr 16th, 2010, 5:24am
 
Count,

You might have noticed your linear PLL transfer functions have unit. And that tells you which noise you should simulate for each block.
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Ken Kundert
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Re: PLL Phase Noise Simulation
Reply #6 - Apr 16th, 2010, 3:04pm
 
PSS/PNoise simulation is needed for certain blocks such as the VCO, the frequency divider, and the PFD/CP. You cannot use a simple SPICE noise analysis with these blocks because the noise they produce with a DC operating point is much different from the noise they produce when actually operating properly.

Once you have all the noise contributors you can generally use a simple AC analysis for the phase domain model that is used to combine all the contributions to predict the output noise.

-Ken
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Re: PLL Phase Noise Simulation
Reply #7 - Jun 17th, 2010, 1:13am
 
I have a related problem here. I modeled all blocks of the PLL in phase domain as stated in the Ken's paper. Used flicker_noise(.,.,.) function to model the noise generated in the oscillator and VCO. However I cannot see the effect of noise in ac simulation. I need to run a noise simulation in cadence to see the effect of noise at any specific point. Now I realized that noise analysis doesn't show the effect of the loop filter and an ac analysis is needed for that.
Anybody has any idea what I should do?

Thanks a lot in advance.
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lunren
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Re: PLL Phase Noise Simulation
Reply #8 - Jun 17th, 2010, 4:50pm
 
Hi Ken or other experts,

Can you give us some hints on these questions?
1) Like Count said that each block in PLL has different beat frequency, should we just use sweeptype=relative for PFD+CP, divider and VCO, and don't care about the fact that each block has different beat frequency?
2) Assume we using phase domain noise model for the PLL. I know we should use pnoise+jitter to get phase noise of VCO (dBc/Hz). Should we also use pnoise+jitter for divider and PFD+CP? If so, I have two pussles:
  a) for divider if jitter feature is used, should we set the stop frequency of sweeprange to half beat frequency or just set it to the offset frequency range of interest and don't care about the noise folding?
  b) for PFD+CP if jitter feature is used, how can we set the threshold value?

Thanks,
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Best Regards,

Lunren
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Mayank
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Re: PLL Phase Noise Simulation
Reply #9 - Jun 21st, 2010, 9:42pm
 
A further to Ken's post. Quote:
PSS/PNoise simulation is needed for certain blocks such as the VCO, the frequency divider, and the PFD/CP. You cannot use a simple SPICE noise analysis with these blocks because the noise they produce with a DC operating point is much different from the noise they produce when actually operating properly.

Once you have all the noise contributors you can generally use a simple AC analysis for the phase domain model that is used to combine all the contributions to predict the output noise.
Certain Blocks like CP, you would say, would generate current noise constantly.
But, in Locked State, that noise enters the Loop( Discrete Time Operation of PFD ) for only certain Time Period, which is the reset delay of PFD.
This makes it a sampled operation. Current noise is sampled every Tcomparision & is visible to the loop for Treset only.
Thus, all effects like Noise Folding come into play.
Hence, the need for PSS / PNOISE instead of normal small signal NOISE analysis.

Quote:
1) Like Count said that each block in PLL has different beat frequency, should we just use sweeptype=relative for PFD+CP, divider and VCO, and don't care about the fact that each block has different beat frequency?
PLL is a completely non-linear system.
If for eg, you take the VCO. For Ease of Understanding, we can say TF of VCO is A*sin(w*t + Φ). Whatever small signal you apply at a Frequency Δf automatically gets upconverted to Fosc +- Δf due to mixing operation (sine multiplication) of VCO.
Hence, the frequency of a signal at LF o/p gets upconverted around Fosc.

If we develop a PLL Model with sine & cosine TFs, it would become too complex & diff. to understand & solve. Hence, we develop a small signal Phase Domain Model in which we take Noise contributions around each block's Periodic Steady-State Operating Frequency(Beat Freq.) & a small signal gain of conversion around It's Beat Frequency. & then we can model each block as a normal tf without any periodic functions like sine or cosine. Makes our lives easier.
Key Point Being, we already took care of Diff. Beat Freqs. & up/down conversion when we take into acc. noise/signal contribution at Different & appropriate Beat Freqs. from diff. blocks.

Quote:
2) Assume we using phase domain noise model for the PLL. I know we should use pnoise+jitter to get phase noise of VCO (dBc/Hz). Should we also use pnoise+jitter for divider and PFD+CP? If so, I have two pussles:
You can use normal Pnoise/Pnoise Modulated analysis for VCO.
For Driven ckts. like PFD/CP & Dividers, you need to perform time-strobed Pnoise.

Quote:
a) for divider if jitter feature is used, should we set the stop frequency of sweeprange to half beat frequency or just set it to the offset frequency range of interest and don't care about the noise folding?
Always, All Noise Folding Effects should be considered. keep Max. Freq. around 50x the OutPut Freq.

Quote:
b) for PFD+CP if jitter feature is used, how can we set the threshold value?
Which Threshold ?

Probably, one of my Length-iest posts.  :P

--
Mayank.
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Jacki
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Re: PLL Phase Noise Simulation
Reply #10 - Aug 31st, 2017, 11:26pm
 
Hi,

  I am thinking if we just do FFT of the output signal from the PLL, and we can get the output phase noise directly. Then we can use the linear model to estimate each part's contribution. Does it make sense?
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sheldon
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Re: PLL Phase Noise Simulation
Reply #11 - Yesterday at 3:58pm
 
Jacki,

  The calculation is more complex. You actually perform a power spectral
density on the absolute jitter. An FFT is good measuring distortion, the
power spectral density is used for measuring noise. See the PLL modeling
white paper for a detail discussion on the topic.
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