// VerilogA for PLLCells, white_noise_source, veriloga `include "constants.vams" `include "disciplines.vams" module white_noise_source(p, n); inout p; inout n; electrical p; electrical n; parameter real mean = 0; parameter real std_dev = 1; parameter real update_freq = 50e9; integer seed; integer state; real update_per,x; parameter real scale = 10e-3; analog begin @(initial_step) begin seed = 1; state = 0; update_per = 1/update_freq; end @(timer(0,update_per)) begin x = scale * $rdist_normal(seed,mean,std_dev); end V(p,n) <+ x; end endmodule
@(timer(0, update_per)) begin x = scale * $rdist_normal(seed, mean, std_dev); end V(p, n) <+ x;