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pole zero doublet in regulator (Read 845 times)
raja.cedt
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Posts: 525
pole zero doublet in regulator
Jan 23
rd
, 2010, 1:03am
hi,
I am designing a simple regulator with nmos input opamp and pmos pass transistor o/p stage. I am getting a pole zero doublet near 100hz.I am attaching both ckt as well as bode plot,so please let me know your thoughts.
Thanks,
Rajasekhar.
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plot_001.png
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raja.cedt
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Re: pole zero doublet in regulator
Reply #1 -
Jan 23
rd
, 2010, 1:07am
here is the plot.
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wave.png
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thechopper
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Re: pole zero doublet in regulator
Reply #2 -
Jan 25
th
, 2010, 4:19pm
Hi Rajasekhar,
What is your regulated voltage level? Is your pass transistor working in triode mode?
One possibility is the capacitance difference between the two branches of the differential pair helping create such doublet.
Best
Tosei
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raja.cedt
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Re: pole zero doublet in regulator
Reply #3 -
Jan 25
th
, 2010, 8:40pm
hi tosei,
tx for your reply. This regulator has designed for 1.2 with .8 reference voltage. You mean the cap at the drains of the diff pair transistors? i didn't understand how they will give,in fact i did many regulators of this sort i didn't see any doublet. What i am thinking is at the first stage o/p i have kept rc seris compensation network, parallel to that pass transistor Cgs is there, i feel this may be the culprit. any how please explain this.
Thanks,
rajasekhar.
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vivkr
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Re: pole zero doublet in regulator
Reply #4 -
Jan 25
th
, 2010, 11:01pm
you've got quite a lot of RC branches in your schematic. Perhaps it would help people answer your question if you specify what these R and C values are. And maybe it would help if we could see the ratio of transistor sizes.
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raja.cedt
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Re: pole zero doublet in regulator
Reply #5 -
Jan 27
th
, 2010, 5:56am
hi vivkr,
sorry for that confusing schematic, the RC what i am talking is at the o/p of the 1st stage.
Thanks,
Rajasekhar.
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yvkrishna
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Re: pole zero doublet in regulator
Reply #6 -
Jan 30
th
, 2010, 11:05pm
hi raja,
i too feel that your RC n/w at the o/p of first stage is causing this. what are the values used here?
btw how would that series RC branch compensate your loop ?
regards,
vamshi
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raja.cedt
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Re: pole zero doublet in regulator
Reply #7 -
Jan 31
st
, 2010, 1:30am
hi vamshi,
i have introduced zero at the 2nd pole to compensate the loop..i am not getting what you are asking?
Thank,
Rajasekhar.
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Berti
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Switzerland
Re: pole zero doublet in regulator
Reply #8 -
Feb 4
th
, 2010, 12:13am
Rajasekhar,
Quote:
am getting a pole zero doublet near 100hz
The doublet is at 100Mhz not 100hz ???
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raja.cedt
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Re: pole zero doublet in regulator
Reply #9 -
Feb 5
th
, 2010, 11:03pm
hi,
how it won't be at around 100hz,there only i saw some dip in the phase plot.
Thanks,
rajasekhar.
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Berti
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Switzerland
Re: pole zero doublet in regulator
Reply #10 -
Feb 8
th
, 2010, 3:44am
Rajasekhar,
100hz is just a very low frequency. Therefore without studying you schematic I cannot see how such a low pole should come from the amplifier as Vamishi suggests.
I think it has to be related with the large load capacitance ...?...
Cheers
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thechopper
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Re: pole zero doublet in regulator
Reply #11 -
Feb 10
th
, 2010, 6:32pm
raja.cedt wrote
on Jan 25
th
, 2010, 8:40pm:
hi tosei,
tx for your reply. This regulator has designed for 1.2 with .8 reference voltage. You mean the cap at the drains of the diff pair transistors? i didn't understand how they will give,in fact i did many regulators of this sort i didn't see any doublet. What i am thinking is at the first stage o/p i have kept rc seris compensation network, parallel to that pass transistor Cgs is there, i feel this may be the culprit. any how please explain this.
Thanks,
rajasekhar.
Hi Rajasekhar,
Take a look at this one yourself asked about...
http://www.designers-guide.org/Forum/YaBB.pl?num=1235622483
Best
Tosei
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Keep it simple
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