When I use the bound_step() command in Verilog-A/HSPICE, it works as expected for timesteps of 2ps and above. When I try to force a timestep smaller than that, the simulator ignores it, and keeps the timestep at 2ps.

I've tried as many .option settings as I can find, and none seem to effect this limit. Using delmax is not an option, as I need the simulation to take longer steps at other parts in the sim, and only want to force the timestep small at key places.

I extracted the simplest example that displays the problem, and attached the files (an input HSPICE file, and Verilog-A module), in case anyone's interested. The Verilog-A code simply decreases the timestep by 10x from 1ns on down, and the result I see is that the minimum timestep stops decreasing at 2ps, even when bound_test() tries to force 1ps,0.1ps,... The output voltage of the module is equal to the timestep, so that you can observe the value that is being set.

Anyone know why this happens?

Thanks, Bob

Hi Pancho,

Yes, I agree with you about the merit of bound_step(), but I think this code shows that it isn't working below 2ps.

Here's my code (sorry the attachment didn't take). It's very short:

HSPICE netlist:
-----------------
*test timesteps
.hdl stepforce.va
.option post
.tran 1p 8n
x1 vtforced stepforce
.end

Verilog-A file: (stepforce.va):
--------------------------------
`include "standard.va"
module stepforce(out);
output out;
voltage out;
real stepsize;
analog begin
 @(initial_step) stepsize=10n;
 @(timer(1n)) stepsize=1000p;
 @(timer(2n)) stepsize=100p;
 @(timer(3n)) stepsize=10p;
 @(timer(4n)) stepsize=1p;
 @(timer(5n)) stepsize=0.1p;
 @(timer(6n)) stepsize=0.01p;
 @(timer(7n)) stepsize=0.001p;
 V(out) <+ stepsize;
 $bound_step(stepsize);
 end
endmodule

I discussed this with a Synopsys support engineer, and he said that all parts of the circuit should see the same timestep. I guess that means that HSPICE is not a multirate simulator (?).

Even if it was multirate, it seems like the simulator should dis-able that, or at least have an option to disable it, if bound_step() is called. Otherwise, how could they claim to be Verilog-A compliant?

Thanks, Bob

Sorry that was unclear. Let me try that paragraph again:

Quote:


What I really mean is that, if bound_step() calls for a certain timestep, the simulator should enforce it, regardless of the simulator's internal algorithms.

Thanks for taking a look at it. - Bob

bobr.spi Quote:

stepforce.va Quote:

bobr wrote on Dec 14^th, 2009, 9:06am:
See title of my right graph.
I used C-2009.03 32bit Version.

To my regret, I can not access C-2009.09.

If there is anyone who can access HSPICE C-2009.09, try to run simulation and show us results.

My environments are :
****** HSPICE -- C-2009.03 32-BIT (Feb 24 2009) linux ******                  
hsp-vacomp: Synopsys HSPICE Verilog-A Compiler Version 1.75.100.013009.