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Ideal voltage source in spectre (Read 9388 times)
rampat
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Ideal voltage source in spectre
Nov 03rd, 2009, 9:32pm
 
Hi

For my test bench I am using ideal voltage source for supply.Now I want to limit the current from  voltage source (like LDO).How can I model this in my testbench..
Is there a LDO model in any of cadence libraries ?

Thanks
ramapt

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rajdeep
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Re: Ideal voltage source in spectre
Reply #1 - Nov 5th, 2009, 4:04am
 
You can use a series resistance to model the output resistance in a way that whenever the current is beyond a certain limit the drop across the resistance becomes quite a significant drop!! If you spectre ideal components then it would be hard to makethe resistance variable. You can use a constant resitance, but that might not suffice your requirement.

You can use Verilog-A to model such a voltage source where you can make the output resistance variable  so that the voltage drop is insignificantly small until the current becomes more than what you  want. At that point  you make the resistance value to change to a larger value to cause a significant drop across the resistor.

hope that helps..
Rajdeep
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jerome_ams
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Re: Ideal voltage source in spectre
Reply #2 - Nov 24th, 2010, 9:31am
 
I agree with Rajdeep: a variable serie resistance is the usual way to get a realistic behavior (you get a significant voltage drop when the current exceed the limit).
Another alternative would be to implement in VerilogA a current limiter, which will clamp the current to a certain value, with no impact on the voltage delivered by your voltage source... This would be a more abstract way, less related to how a "real" LDO would behave. It depends what u need.

Cheers,
jerome
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Geoffrey_Coram
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Re: Ideal voltage source in spectre
Reply #3 - May 13th, 2015, 8:31am
 
It's really hard to implement a current-limiter in a way that doesn't cause convergence problems.
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