jerome_ams
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I agree with Rajdeep: a variable serie resistance is the usual way to get a realistic behavior (you get a significant voltage drop when the current exceed the limit). Another alternative would be to implement in VerilogA a current limiter, which will clamp the current to a certain value, with no impact on the voltage delivered by your voltage source... This would be a more abstract way, less related to how a "real" LDO would behave. It depends what u need.
Cheers, jerome
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