loose-electron
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Best Design Tool = Capable Designers
Posts: 1638
San Diego California
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The problem is one of tolerable limits.
Max resistance - what will simulations tell you is tolerable in both max L and max R in the interconnect.
Min resistance/inductance - for present placements of components, whats the lowest resistance interconnect tht can be placed?
If you can get an interconnect in place between those two you should be fine.
Also, make a check of you contact resistance and via resistance. These can be significant.
Generally, its not too much of a problem, until you are dealing with high current circuits (amperes of current on the chip) Or high frequencies (100MHz, 60GHz, etc.), where the RLC of the network becomes critical.
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