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Abt CADENCE VERILOG-XL PROBLEM (Read 9476 times)
VINAY RAO
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Abt CADENCE VERILOG-XL PROBLEM
Sep 17th, 2009, 3:30am
 
HI,
   I am facing many problems while openening VERILOG-XL in CADENCE.If  i am going to V-XL through schematic (as tool-simulation-verilog-xl-setup enironment-run directory(ex:mos.run1)) after setup env's ok ,its showing the error as "INVALID VERILOG EXECUTABLE VERILOG,Please check existance and for permissions and try again,relative path names are relative run directory"...If i clsose the simulation option warning then verilog-xl window is opening..after setng up the environment and start interactive(simulation) in between error is coming..That error is "user-settable variable:verilogsimbinary is invalid.,Relative path names are relative to run directory"..
simulation is gtng aborted.If i am opnng directly thru the CIW window its shwng the same prob..
Hw cn i solve this prob???.
Pl reply soon,,pl if u dnt know ,pl ask ur administrator and help me..i am runnng out of time in my project...Its my humble request..
Thank you..

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Andrew Beckett
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Re: Abt CADENCE VERILOG-XL PROBLEM
Reply #1 - Nov 30th, 2009, 10:04am
 
First of all, apologies for the delay in responding.

I suspect most people will have been put off responding by the rather unreadable nature of your post (please don't use "text message" type language, as it is very hard to read, and there's no tax on characters in an on-line forum). I had to read it several times to decrypt what you said (I must be getting old...)

Anyway, the most likely explanation is that  you don't have the simulator "verilog" in your UNIX path. At the UNIX prompt, you'd need to be able to see a result if you type "which verilog".

That said, it really makes little sense using Verilog XL. This has been obsolete for many years - better to use the NC Verilog interface instead. You'll also need that in your path - both come from the IUS stream (now called INCISIV92 in the latest release).

Best Regards,

Andrew.
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