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design of ASIC CMOS opamp
Jun 08^th, 2009, 11:27am

Hi

I am designing an application specific CMOS op-amp which has very stringent requirements.
I am starting with a basic 2-stage topology
Some of the requirements would be :
1. Unity gain Bandwidth > 500MHz (Also in feedback my opamp needs to have a 3dB Bandwidth of > 25MHz)
2. High gain >75dB
3. Another very important requirement of my design is tht the biasing of my op-amp is independent of the feedback circuitry .
4. I am using Vdd = 3.3 V and Vss = -3.3 V (0.6 um tech). If i maintain my input common mode level at 0V i need my output dc level to be at 0V too.

I would really appreciate if any of you could provide me any inputs on these.

thanks

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raja.cedt

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Re: design of ASIC CMOS opamp
Reply #1 - Jun 8^th, 2009, 4:55pm

hi,
i think it is prety easy,
1. From your first spec you can say find max feedback gain or closed loop gain.
2.75db is very straight forward in case of cascode and folded cascode, you try with this you may get 75 DB very easily because .6um tech and large power supply. If you are not getting 75db then go for 2nd stage and if so dont put too much gain in the 2nd stage.
3.I didn't understand this point.
4. Use folded cascode because you want both input and output common mode are decoupled.

Hope you find some useful stuff here.
thanks,
Rajasekhar.

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carporsche

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Re: design of ASIC CMOS opamp
Reply #2 - Jun 8^th, 2009, 8:03pm

Thanks raja.cedt for your replies

Ok let me get more specific with the issues.

The 1st 2 points do not pose a very big problem and am sure it can be achieved.

The op-amp i need needs a buffered output stage (low impedance output). The op-amp needs to be in a non-inverting configuration . It'll be drawing current from a range of uA to mA over a particular frequency range.

So the problem statement here is : I can put in a common mode level to the +ve terminal to keep tht input transistor in saturation(and then put in my ac signal on top of it ), but how do i make sure the negative input transistor is also at the same dc level(i.e in saturation).

I may be a little confused here and correct me if i am wrong, But now when using the op-amp in the non-inverting configuration the biasing of the negative input transistor will depend on the output DC level and the feedback impedance values. Am I thinking right here?..

In contrast when using a discrete BJT op-amp (like the 741) we do not have to worry about this above mentioned issue.

Am not really sure and would like further clarifications with respect to CMOS op-amps. If anyone can help.

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raja.cedt

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Re: design of ASIC CMOS opamp
Reply #3 - Jun 8^th, 2009, 9:29pm

hi,
can you give complete spec so that people may think more about your problem.
I think for your application two stage op amp will be good, single stage you cant drive mA load. whenever you put op amp in the -ve feedback then opamp inverting terminal will try to follow non inverting terminal but some times it fail because output common mode and input common mode is differ by large value, so while designing make sure that both are equal. Lets say you have 650mv at input and 1v is the ouput common mode then in the -ve feedback opamp offset voltage will be 350mv/(open loop dc gain).

thanks,
Rajasekhar.

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