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DAC's phase noise (Read 8253 times)
maxiao0116
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DAC's phase noise
Apr 08th, 2009, 8:39am
 
i want to simulate the phase noise of a 14bit Didigtal to Analog Converter .
but i am not sure if my pss and pnoise configurations are right

i use a digital module to generate a 80MHz sinewave data and pass it to the DAC, DAC and digital module are
both using 400MHz sampling frequency. The final differential outputs from DAC is a 14bits 80MHz square wave.

i set the pss fundamental freq to 400MHz and beat freq to 80MHz,  15 harnomics. The PSS converged after 11 iterations.

my question is
1. are those configurations right? i got a pnoise plot from 100Hz@-130dBc/Hz downto 10MHz@-140dBc/Hz, almost flat!
2. what can i do if i want to simulate a 160MHz output frequency which doesn't have integer multiples with 400MHz sampling frequency
3. what type of noise i should use in Pnoise Analysis, source?jitter?, i used source.
4. if i combine the digital module and DAC together (sampling clock is generated from digital module in verilog), it seems like an oscillator,
Can i use the "Noise aware PLL flow" to  convert the whole circuit to PPV based behaviour module ?

thanks
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pancho_hideboo
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Re: DAC's phase noise
Reply #1 - Apr 10th, 2009, 7:59pm
 
maxiao0116 wrote on Apr 8th, 2009, 8:39am:
i set the pss fundamental freq to 400MHz and beat freq to 80MHz
No. You are wrong. Fundamental frequency is 80MHz in your case.
See http://www.designers-guide.org/Forum/YaBB.pl?num=1232036048/4#4

maxiao0116 wrote on Apr 8th, 2009, 8:39am:
1. are those configurations right?
i got a pnoise plot from 100Hz@-130dBc/Hz downto 10MHz@-140dBc/Hz, almost flat!
I think your settings must be wrong for both PSS and Pnoise.

How do you set "sweeptype" in Pnoise ?
You should set like followings.
 aho  pss  fund=80M  harms=0  maxacfreq=4G errpreset=moderate annotate=status  outputtype=time
 boke pnoise start=10 stop=100M dec=11 maxsideband=50
 + sweeptype=relative relharmnum=1 annotate=status  

maxiao0116 wrote on Apr 8th, 2009, 8:39am:
2. what can i do if i want to simulate a 160MHz output frequency which doesn't have integer multiples with 400MHz sampling frequency
You don't seem to understand PSS analysis.

There is no problem if you set 80MHz as Fundamental frequency in PSS.
160MHz=2*80MHz, 400MHz=5*80MHz.
In this case you have to set relharmnum=2.

maxiao0116 wrote on Apr 8th, 2009, 8:39am:
3. what type of noise i should use in Pnoise Analysis, source?jitter?, i used source.
It is dependent on your interest.

maxiao0116 wrote on Apr 8th, 2009, 8:39am:
4. if i combine the digital module and DAC together (sampling clock is generated from digital module in verilog), it seems like an oscillator,
Can i use the "Noise aware PLL flow" to  convert the whole circuit to PPV based behaviour module ?
I have no answer for this since I'm not Cadence Tool's Player.

Some Cadence guys in this forum, e.g. sheldon, Andrew Beckett, Tawna Wilsey might answer for this.
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« Last Edit: Apr 11th, 2009, 2:22am by pancho_hideboo »  
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Andrew Beckett
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Re: DAC's phase noise
Reply #2 - Apr 12th, 2009, 8:27am
 
maxiao0116 wrote on Apr 8th, 2009, 8:39am:
4. if i combine the digital module and DAC together (sampling clock is generated from digital module in verilog), it seems like an oscillator,
Can i use the "Noise aware PLL flow" to  convert the whole circuit to PPV based behaviour module ?

I don't really see why you think it's like an oscillator? It's not autonomous, is it? Or perhaps I've misunderstood your circuit...

Regards,

Andrew.
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sheldon
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Re: DAC's phase noise
Reply #3 - Apr 12th, 2009, 9:15am
 
Max,

  Some additional comments,

1) Why is the output a square wave? As Panchoo Hideboo commented
   the choice of frequencies is probably not appropriate. Attached is
   an example using the results for PSS analysis of a DAC using the
   setup described in previous appends related to ADC test setup.

   Note: The DAC output should be a sine wave if the input is a
            sine wave. In this case, the time domain waveform is not  
            shown, however, it was a sine wave as can be seen by the
            output spectrum.
       

2) The circuit is driven, using autonomous analysis is not is not
   appropriate.

3) The Noise-Aware PLL flow supports PLL simulation and is not
    appropriate for this case.



                                                              Best Regards,

                                                                 Sheldon
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maxiao0116
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Re: DAC's phase noise
Reply #4 - Apr 12th, 2009, 10:59pm
 
Thank you very much pancho hideboo. i think i misunderstood "beat freq" and "funda freq".
i should use such fundamental frequency whose multiples can represent all the frequency components in real spectrum, is that right?
if i want to get PSS solution for a 160MHz outputs, i should use 80MHz whose 2nd harnomics is the actual signal, and 5th harnomics is clocking feedthrough.

To Andrew Beckett:
 My system is a Direct Digital Synthesizer, it tunes the output frequency by just modifing the digital "Frquency Ctrol Word", like F = Kvco*V in digital, expect a constant sampling frequency should be provide in addition.

 if i encapsulate the digital part, DAC and sampling frequency source, i can pin to pin match a typical VCO symbol, and also the general functions.

 i am wondering if it's work because it's very time consuming to simulate the DDS's narrow band spurs.

To sheldon:
     i think i made a misunderstanding, the "square wave" i mentioned is acutally "sine weighted square wave". I say it square because the output is not filtered by LPF yet. I got a similar SFDR plot like you.
     I know it's not an autonomous system, but can i force it to use perturbation vector if i encapsulate the whole system to a pin2pin matched vco in Noise-Aware PLL flow and finish all the required simulations in that flow?

Thank you all.
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