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The Designer's Guide Community Forum › Design › Analog Design › Ripple in the control voltage of PLL for high gain and low i/p frequency

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Ripple in the control voltage of PLL for high gain and low i/p frequency (Read 1749 times)

pkd

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Ripple in the control voltage of PLL for high gain and low i/p frequency
Mar 14^th, 2009, 11:56am

Hi all,
I am simulating my PLL which is intended to work for an input frequency of 1MHz and has to provide a frequency gain of 512 (i.e. the feedback loop divider has 512 stages.)
With this settings while simulating in cadence over many cycles, I get a ripple on the control voltage of the VCO which has a frequency same as �the input frequency of the PLL. This effect is not visible while simulation with the matlab models.In fact I am testing the chip where this exact effect is noticed.For lower frequency gain there is no issue; but for higher gain this ripple comes up.
Can anybody provide any information on the cause of this phenomenon and possible solutions for this?
Regards,
pkd

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buddypoor

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Re: Ripple in the control voltage of PLL for high gain and low i/p frequency
Reply #1 - Mar 14^th, 2009, 3:29pm

It�s not easy to answer, as there is not enough information available:
-What kind of PD ?
-What are the model differences between Cadence and Matlab ?
-Do you work with different VCO�s for different frequency gains or with different input frequencies ?
-Are you always in a locked state ?

LvW (buddypoor: In memory of the great late Buddy Rich)

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pkd

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Re: Ripple in the control voltage of PLL for high gain and low i/p frequency
Reply #2 - Mar 14^th, 2009, 4:53pm

Dear buddypoor,
These are some further information answering to your questions.

The PD is a conventional one (PFDs discussed in text books).
Cadence models are transistor level models, where as matlab models are based on some previously described models of PLL.
I work with the same VCO for different frequency gains.I change the divider and the LPF part only for changing the frequency gain.
Yes, I am always in the locked state, but as the control voltage to the VCO carries a ripple there are significant components around the central peak frequency. (E.g. I get frequency to be hopping between 510MHz and 514MHz with a period of 1us for an input freq of 1MHz and the freq gain of 512)

Hope the question become more clearer now.
-pkd

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Visjnoe

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Re: Ripple in the control voltage of PLL for high gain and low i/p frequency
Reply #3 - Mar 15^th, 2009, 12:35am

Dear pkd,

most likely you are seeing the reference spur, which can be caused by the finite mismatch between UP/DN currents in your charge pump.
Other possible sources of mismatch might be different delays for the UP/DN signal path etc.

Introduce in your Matlab model some mismatch in your PFD/CP model and you will see this reference spur pop up.

Regards

Peter

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buddypoor

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Re: Ripple in the control voltage of PLL for high gain and low i/p frequency
Reply #4 - Mar 15^th, 2009, 1:49am

pkd wrote on Mar 14^th, 2009, 4:53pm:

Dear buddypoor,
These are some further information answering to your questions.

The PD is a conventional one (PFDs discussed in text books).
Cadence models are transistor level models, where as matlab models are based on some previously described models of PLL.
I work with the same VCO for different frequency gains.I change the divider and the LPF part only for changing the frequency gain.
Yes, I am always in the locked state, but as the control voltage to the VCO carries a ripple there are significant components around the central peak frequency. (E.g. I get frequency to be hopping between 510MHz and 514MHz with a period of 1us for an input freq of 1MHz and the freq gain of 512)

Hope the question become more clearer now.
-pkd

Maybe that the loop filter causes some problems since you are changing its characteristics each time you change the frequency.

LvW (buddypoor: In memory of the great late Buddy Rich)

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Berti

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Re: Ripple in the control voltage of PLL for high gain and low i/p frequency
Reply #5 - Mar 16^th, 2009, 3:39am

I agree with Peter. There is always a ripple on the reference voltage - you just make sure that it is small enough that the resulting reference spur is within your specifications.

If you haven't analyzed charge-pump artifacts yet (mismatch, rise time, dead-zone etc.) I recommend to do it now.

Cheers

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pkd

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Re: Ripple in the control voltage of PLL for high gain and low i/p frequency
Reply #6 - Mar 16^th, 2009, 7:12pm

I believe these problems like finite mismatch between UP/DN currents in the charge pump and delay mismatches would be consistently there for any input frequency and any frequency multiplication ratio.
Can there be any reason for them to be higher at lower input frequency and/or higher multiplication ratio?If yes, is there any possible solution for that?
Thanks,
pkd

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Berti Community Fellow Offline Posts: 356	Re: Ripple in the control voltage of PLL for high gain and low i/p frequency Reply #7 - Mar 17^th, 2009, 4:50am Hi pkd, The magnitude of the spurs also depend on the divider ratio. Read e.g. Keliu Shu's Book CMOS PLL Synthesizer. Cheers
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Visjnoe Senior Member Offline Posts: 233	Re: Ripple in the control voltage of PLL for high gain and low i/p frequency Reply #8 - Mar 17^th, 2009, 5:53am I agree. The power of the spurs should scale with N^2 with N being your divider ratio. Regards Peter
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pkd Junior Member Offline Posts: 25 India	Re: Ripple in the control voltage of PLL for high gain and low i/p frequency Reply #9 - Mar 18^th, 2009, 10:37am Oh... Then how can I get the higher frequency gain? �:-[ Is there any published method for getting such a frequency gain of around 500-1000 for lower frequencies like 1MHz? And yes...is there any roll of input frequency for this behavior? Thanks! -pkd
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subgold

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Re: Ripple in the control voltage of PLL for high gain and low i/p frequency
Reply #10 - Mar 18^th, 2009, 12:39pm

pkd wrote on Mar 18^th, 2009, 10:37am:

Oh...
Then how can I get the higher frequency gain? �:-[
Is there any published method for getting such a frequency gain of around 500-1000 for lower frequencies like 1MHz?
And yes...is there any roll of input frequency for this behavior?
Thanks!
-pkd

it is inversely proportional to the input frequency.

how large is your reference spur in terms of dbc? I dont think you can completely get rid of it, but with optimization of the mismatch and deadzone of your PFD, and careful design of the loop filter (selection of pole location, or use a notch filter), you may improve it. you may also try to inject a periodic compensation signal to reduce the influence of the PFD nonideality.

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