SG
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Hi,
I have been using verilog-xl so far and have got my code compiled in the format where I use the same module with different bit-widths and get it compiled.
For eg, quantizer #(32,16) quant1(out,in)
I now need to generate some annotation files using nc-verilog and hence, when I compile the same in it, it gives me an error, with the "#(32,16)" part: Too many module instance parameter definitions.
Is it possible to make nc-verilog read the above statement without having several copies of the same module in my code ?
Thanks for you help, Shubh.
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