Hi,
Quote:or you can filter your continuous output thru an $absdelay filter..
I tried to delay a voltage input while running a transient simulation. It looks like the following.
Code:electrical vin;
realy vin_delay;
vin_delay = absdelay(V(vin),10n);
The spectre simulator reported the following warning message.
Warning from spectre during AHDL read-in.
"/export/home/myhome/work_libs/dac_inl_10bit/veriloga/veriloga.va", line 87: Warning: '(abs)delay()" does not account for phase shift in small-signal analysis.
What does that mean?
Thank you in advance.
Yawei