Static phase offset is the time difference between the averaged input reference clock and the averaged feedback input signal when the PLL is in locked mode. The word average implies that a comparison is made between the input of the PLL and its feedback over several thousand periods, and the resulting time differences are averaged. This method excludes jitter components, hence the name static phase offset.

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If you don't mind me continuing the discussion, I'm trying to build up my intuition for this stuff...

Can I think of static phase error as the equivalent of skew in a clock tree?  Two signals, refclk & synthclk in this case, with a constant offset?

Will a pll have a relatively constant static phase error over a frequency range, or is it really a fixed time interval?  If the latter, I'd expect the static phase error of the pll to increase with frequency, as the clock period gets smaller relative to the offset.  Am I thinking about this right?

How does deadband behave?  I'm imagining the instantanious phase error would slowly increase until it bumps into the end of the deadband, where the PLL will give it a nudge and it will start drifting to the opposite side of the deadband, rattling back and forth so to speak.  What sort of patterns might I see when measuring period or phase-error vs. time?

I hope these questions are clear enough to be worth answering.  This is confusing stuff for me. Thanks!