If you have a high frequency stimulus it is possible for the simulator to completely miss it because of aliasing. When I was developing Spectre this happened in the first transient analysis I ran. The source produced a 1MHz sinewave, the simulation interval was 100 μs, and Spectre started by taking a step 1% of the simulation interval. In doing so it happened to sample the signal at its zero point after the first period, so it did not sense any change in the circuit, so it continued taking the same step, each time seeing no activity. The computed result was a flat line. I hunted around for quite a while before I realized what the problem was. When I found it I added the bound_step feature. The sine source uses it to tell kernel not to take a time step larger than a quarter period of the sinusoid. In this way the simulator is guaranteed to notice the input signal. It can then use its normal timestep control to get an accurate answer.

So, if you build a Verilog-A model that is time varying (like all sources are) you must be aware of this issue. This is particularly true with time variations that are smooth (as a sinusoid is). It is discussed on page 77 of my Verilog-AMS book. To solve this problem you use the $bound_step function in the source. The bound itself can vary with time, which helps if the source turns off or changes frequency.

-Ken

bound_step() is not like maxstep. maxstep bounds all time steps, bound_step() only bounds the current step. So if you used
@(initial_step) $bound_step(1n);
you would only be placing a bound on the first time step.

-Ken

No. Spectre, along with all Spice-like simulators, dynamically adapt their time step to the activity currently present in the circuit. But if you write a behavioral model that acts like a high frequency source you need to bound the timestep. If you don't, aliasing can occur that is not detectable by Spectre, or by any simulator. You don't have to "control" the timestep for Spectre. For example, to get a good result, you typically need at least 10-20 timepoints per cycle of an input sinusoid. However, you don't need to bound the step to 0.1T or 0.05T. It is sufficient to bound the step to 0.3T. With that bound it is not possible to undersample the waveform and produce a constant-valued waveform. Rather, the waveform will vary on a per step basis, and then the simulator will observe the variation and then shrink the step automatically to render the waveform accurately.

-Ken

Did you use a cross statement on the clock input in your sigma-delta Verilog-A code to detect the clock edge?

Rajdeep

Hi Ken,

Thank you very much for so much good advices.  

This is a sigma-delta modulator. The opamps, switches, and all logic gates are written in Verilog-A language. They are the cells in ahdlLib or bmslib. I want to set up a testbench using those cells to reduce the simulation time at the initial stage of the design.

Part of the circuit is shown below. For example, an ideal pulse voltage source is fed to the input of a xor/xnor gate. Other pulse sources go to corresponding logic gates like NAND and NOR. One part of its verilog-A code for xor/xnor gate is listed here.

Code:

	@ (cross(V(vin1) - vtrans, 1))  logic1 = 1;
	@ (cross(V(vin1) - vtrans, -1)) logic1 = 0;

	@ (cross(V(vin2) - vtrans, 1))  logic2 = 1;
	@ (cross(V(vin2) - vtrans, -1)) logic2 = 0; 

I belived the cross function must affect the time step. But it obviously failed.

I tried two spectre versions. One is spectre of sub-version  7.1.1.187.isr11.  The other is spectre of sub-version 5.10.41_USR6.081308.


Best Regards,
Yawei

Sheldon,

Thank you. That's what I need.

Yawei

Hi Rajdeep,

You are right. The bigger the design is the explicit tolerance declaration becomes more important. I don't know the reason. But it seems true in my simulations.

Another point is that the longer stop time is for tran analysis, the explicit tolerance declaration becomes more important.


Yawei