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neoflash Community Fellow Offline Mixed-Signal Designer Posts: 397	PFD reset path mismatch Oct 05^th, 2006, 11:18am Hi: For bang-bang PFD, what will happen if up/dn reset path is not symetrical? anything more than a static phase offset?
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: PFD reset path mismatch Reply #1 - Oct 11^th, 2006, 10:51pm Statice phase error will be the big one I beleive. A lot of PFD are donw with timing that you get a small PU and a small PD when the device is in "perfect phase" this minimizes the so-called deadbanding and miismatch problems when these pulses decrease to zero time periods.
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vivkr

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Re: PFD reset path mismatch
Reply #2 - Oct 20^th, 2006, 5:31am

Hi,

Maybe I am wildly off the mark but I can see another subtle effect if the
UP/DN paths are not symmetrical:

limit cycles in the VCO frequency may arise because of the following effect:

1. As the phase error goes close to zero, there is a net charge delivered to the loop filter which
would not happen if the UP/DN pulses were symmetrical. Firstly, this will cause static phase error.

2. Secondly, depending on the dynamics of your loop, you may be pushing your PLL out of its stable
range. To see this, consider that the gain of the PFD increases for phase errors close to zero as the
amount of charge dumped onto the loop filter does not scale down linearly with the phase error, and
tends to be higher than what you would get from a linear scaling. Thus, the gain of the path is different
from the gain assumed when doing stability analysis. Thus, the loop is pushed away from its stable
point as it closes in onto the zero phase error point.

3. Since the loop returns to its normal stable state as soon as the phase error is a little larger, the stability
is restored, and you get limit cycles and not a full-blown oscillation, which result in frequency modulation of the VCO frequency. I expect that
the effect should be quite small though. Besides, this will only happen if the loop is unstable for the increased PFD gain.

Comments are invited from PLL experts !!!

Regards
Vivek

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ywguo

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Re: PFD reset path mismatch
Reply #3 - Oct 22^nd, 2006, 8:15pm

Hi Vivek,

I designed several PLLs, all with PFDs without dead-zone. That is conventional PFD design, which makes UP/DN almost symmetry and linear to the phase error. However, it always has a little amount of charge delivered to the loop filter. I know that is due to UP/DN current mismatch. So sometimes I think the VCO gain should be small if I want to design a low-jitter PLL. Am I right?

The PLLs I designed are all programmable and with wide VCO range, high VCO gain. I have been troubled by the large jitter. Period jitter is rms 15ps - 20ps.

Best regards,
Yawei

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vivkr

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Re: PFD reset path mismatch
Reply #4 - Oct 22^nd, 2006, 11:45pm

Hi Yawei,

I am no PLL expert as mentioned above

Besides, I was talking of PFD+CP gain.

However, I would say yes, the VCO gain should be as low as possible (while meeting required
range and other specs) to reduce jitter from it. Intuitively, it would seem that for a given
VCO frequency, the lower the gain, the less sensitive it would be to noise on its input.

Besides, the period jitter you mention is useful only if you also specify the VCO frequency.
Maybe, then someone (a PLL expert) can suggest a solution to your jitter problem. I don't
think that a small UP/DN current mismatch would cause you big problems, but I maybe wrong.

Regards
Vivek

ywguo wrote on Oct 22^nd, 2006, 8:15pm:

Hi Vivek,

I designed several PLLs, all with PFDs without dead-zone. That is conventional PFD design, which makes UP/DN almost symmetry and linear to the phase error. However, it always has a little amount of charge delivered to the loop filter. I know that is due to UP/DN current mismatch. So sometimes I think the VCO gain should be small if I want to design a low-jitter PLL. Am I right?

The PLLs I designed are all programmable and with wide VCO range, high VCO gain. I have been troubled by the large jitter. Period jitter is rms 15ps - 20ps.

Best regards,
Yawei

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David Lee

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Re: PFD reset path mismatch
Reply #5 - Oct 23^rd, 2006, 12:46am

ywguo wrote on Oct 22^nd, 2006, 8:15pm:

Hi Vivek,

I designed several PLLs, all with PFDs without dead-zone. That is conventional PFD design, which makes UP/DN almost symmetry and linear to the phase error. However, it always has a little amount of charge delivered to the loop filter. I know that is due to UP/DN current mismatch. So sometimes I think the VCO gain should be small if I want to design a low-jitter PLL. Am I right?

The PLLs I designed are all programmable and with wide VCO range, high VCO gain. I have been troubled by the large jitter. Period jitter is rms 15ps - 20ps.

Best regards,
Yawei

Reducing UP/DN current mismatch can sometimes help. Are you observing a large static phase offset? Reducing VCO gain and period jitter, noise in charge pump as well as loop filter can help. Cause of excessive PLL jitter can be due to any one of PFD/CP, LF, VCO, etc. Why so sure the cause is charge pump current mismatch?

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- David

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ywguo

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Re: PFD reset path mismatch
Reply #6 - Oct 24^th, 2006, 7:12pm

Hi David,

I thought of UP/DN current mismatch because they were always unequal in SPICE simulation. So it induced very small ripple of the control voltage of VCO.

You are correct. Any noise in PFD, CP, LPF, and VCO causes jitter. However, there must be a large static phase error due to UP/DN current mistmatch. I will try to measure the phase error in next design.

BG
Yawei

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loose-electron

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Re: PFD reset path mismatch
Reply #7 - Nov 13^th, 2006, 9:53am

Jitter in a PLL can come from a bunch of different sources, and they all need to be considered:

A partial list that I can think of off the top of my head (and some suggested fixes)

Ground noise coupling into the delay cell. (keep it differential and a current source at the bottom to isolate the delay element)

Power noise coupling into the delay cell.
(put an internal voltage regulator over the ring oscillator to keep this quiet)

Noise coupling into the VCO control line (filter inside the chip, not outside)

Noise coupling between stages of the delay cells in the VCO (layout with good attention to grounding and substrate contacts, and localized HF filtering very close to each cell)

Noise coupling between delay cells thought the VCO control line (localized filter to remove this transition path)

Imbalance of capacitive paths between delay cells. (fix the layout)

Transitioning the delay cell before it has an opportunity to settle out fully again. (Architect to allow the cell to sit stable for a while before transitioning again)

Slew rate of the delay cell transitions being a long slope (edge to edge jitter is a product of two things, noise on the signal and the slope of the signal as it transistions.)

Charge injection in the charge pump structure (use an balanced H-bridge current steering architiecture, compensation for charge injection and the follower op-amp to stransition the current steering switches to similar voltage to what goes into the charge pump.)

And the list goes on and on and on.....

I need to write a book!

Grin

Jerry

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ywguo

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Re: PFD reset path mismatch
Reply #8 - Nov 13^th, 2006, 9:28pm

Hi Jerry,

A very good list.

Quote:

Noise coupling into the VCO control line (filter inside the chip, not outside)

I agree on the above point. I always use on-chip cap of several hundreds of pico-farads for those clock synthesis PLLs. However, some high performance PLLs for RF application have external caps when it needs a very huge cap. Does it have noise coupling issues?

Thanks
Yawei

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loose-electron

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Re: PFD reset path mismatch
Reply #9 - Nov 27^th, 2006, 12:38pm

Quote:

A very good list.

Thanks, the product of "lots of learning experiences" so to speak.
Quote:

I agree on the above point. I always use on-chip cap of several hundreds of pico-farads for those clock synthesis PLLs. However, some high performance PLLs for RF application have external caps when it needs a very huge cap. Does it have noise coupling issues?

Yes it is an issue if it is in a mixed signal environment. In an RF design, if it is on the leadframe in any form it will talk into the LNA front end and into the VCO.

One of the reasons that a lot of RF front ends still exist on stand alone chips.

Jerry

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Jerry Twomey
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